Anritsu Corporation

Kazuhiro Fujinuma

Kazuhiko Yamaguchi

Kazuhiro Yamane

Satoru Shiratsuchi

Sumio Saito

Takeshi Wada

Wataru Aoba

To set an optimum offset voltage and detect an NRZ signal with a very small amplitude. An NRZ signal amplifying deviceincludes: input-side voltage detection meansfor detecting a high-level voltage and a low-level voltage of an input signal to the main amplifier; output-side voltage detection meansfor detecting the two signals inverted relative to each other; and offset voltage control meansfor calculating a center voltage between the detected high-level voltage and low-level voltage, setting an offset voltage at which the center voltage is the center of an appropriate input range of the main amplifierto the offset circuit, and finely adjusting the offset voltage, such that a voltage difference between the detected two signals inverted relative to each other and a polarity change point is close to 0.

NRZ signal amplifying device and method, and error rate measurement device and method

It is an object of the present invention to provide a data signal generating apparatus which is small in size, and can output the serial data in a desired sequence without assuming an indefinite state as well as being capable of dealing with the jitter measurement. In the data signal generating apparatus according to the present invention, synchronization meansfor synchronizing a data output unitwith a multiplexerhas a phase comparatorfor comparing the phase of a data synchronization clock signal outputted from a data output unitin synchronization with the timing to update parallel data, with the phase of a divided clock signal A produced by dividing the frequency of a reference clock signal CKby a plural number 'm' in the multiplexer, the signal A being used for determining the timing to performing parallel-serial conversion, a variable delay devicefor adding a desired delay to a data request signal A', the variable delay devicebeing constituted by an orthogonal modulation type delay device, and a control unitfor controlling a direct control signal to be inputted into the variable delay deviceon the basis of a comparing result obtained from the phase comparatorto synchronize the timing to have the data output unitupdate the parallel data with the timing to have the multiplexerperform parallel-serial conversion processing.

Data signal generating apparatus

The object of the present invention is to provide a data decision apparatus and an error measurement apparatus which can set the phase of the clock to the optimum state with respect to the data signal without continuously sweeping of the phase, and can keep the state for a long time. The data decision apparatus according to the present invention comprises a delay device () for delaying a data signal (Dc) outputted from a decision device () by one bit, a first phase detector () for detecting a phase difference between a data signal (Db) to be inputted to the decision device () and the data signal (Dc) outputted from the decision device (), a second phase detector () for detecting a phase difference between the data signal (Dc) outputted from the decision device () and a data signal (Dd) outputted from the delay device (), a third phase detector () for outputting a base voltage with respect to the output values of the first and second phase detectors (and), and a phase controller () for controlling a phase shift amount of a variable delay device () to equalize an output value (P) of the first phase detector () to a center value between an output value (P) of the second phase detector () and the base voltage (P).

Data decision apparatus and error measurement apparatus

The object of the present invention is to provide a waveform shaping device and an error measurement device which can perform a waveform shaping operation with the sufficient amplitude margin, even if the mark ratio of the inputted data signal is significantly varied and the amplitude of the inputted data signal is decreased. The waveform shaping device according to the present invention comprises a voltage detector () for detecting an inputted data signal (Da) to obtain an amplitude value and the center amplitude voltage of the inputted data signal (Da), a reference voltage generator () for generate the reference voltage corresponding to the center amplitude voltage, and a comparator () for comparing the inputted data signal (Da) with the reference voltage, and in which the waveform shaping device further comprises a correction information outputting section () for outputting correction informationV on the basis of a mark ratio (M) and an amplitude of the inputted data signal (Da), the correction informationV used to correct the center amplitude voltage detected by the voltage detector (), and a correction section () correct the reference voltage or the inputted data signal to be inputted to the comparator () on the basis of the correction information (V).

Waveform shaping device and error measurement device

A data signal generating apparatus with a data output unit for outputting m-bit parallel data and a data synchronization clock signal synchronized with the parallel data in response to a data request signal produced by dividing the frequency of a reference clock signal by 'm.' An m:1 multiplexer for receiving the parallel data in response to a latch signal produced by dividing the frequency of the reference clock signal by 'm,' and outputting, at a rate of the reference clock signal, data synchronization serial data. Synchronization means for comparing the phases of the data synchronization clock signal and the latch signal, for synchronizing the parallel data with the latch signal, and for producing a control signal, and which delays, on the basis of the control signal, the reference clock signal or a divided clock signal (dividing the frequency of the reference clock signal by &#x201c;m&#x201d; or less).

A quadrature modulator divides a first signal input as a local signal into an I channel signal and a Q channel signal orthogonal to each other and outputs a second signal having a desired phase delay corresponding to direct current voltages as for the first signal by giving the direct current voltages Vi and Vq to the I channel signal and the Q channel signal, respectively. A phase comparison unit detects a phase difference &#x3b8; between the first signal and the second signal. A setting unit sets the desired phase delay. A controller section controls the direct current voltages supplied to the I channel signal and the Q channel signal respectively in the quadrature modulator so that an output value corresponding to the phase difference &#x3b8; detected by the phase comparison unit is equal to a value corresponding to the desired phase delay set by the setting unit, and controls the direct current voltages to be the direct current voltages Vi and Vq satisfying the relation of Vi=cos &#x3b8; and Vq=sin &#x3b8;.

Quadrature modulator with phase controller apparatus and error detector

A digital signal offset adjusting apparatus has a capacitor causing an output terminal to pass a high frequency band of an input digital signal. A first coil has one end connected to an input terminal and a second coil has one end connected to an output. An operational amplifier has an input connected to another end of the first coil, a second input connected to a direct current voltage generator and an output connected to another end of the second coil. The operational amplifier outputs a signal obtained by subtracting and combining the low frequency band, the direct current component and a direct current bias voltage. A frequency characteristic compensating circuit is connected between a reference point and the second input of the operational amplifier. The gain of the operational amplifier increases with a component having a higher frequency from among low frequency bands of the input digital signal.

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Ebina, Japan

Kazuhiro Fujinuma