Sumitomo Electric Industries, Limited

Toyohashi University of Technology

Hitachi Maxell, Limited

National University Corporation Toyohashi University of Technology

Kazuhiro Fujikawa

Shin Harada

Satoshi Hatsukawa

Takashi Ohira

Nobuo Shiga

Kenichi Hirotsu

Takashi Hoshino

Kazuyuki Wada

Tsunenobu Kimoto

Hiroyuki Matsunami

Kazuya Ishioka

Tuya Wuren

Takeyoshi Masuda

Hideto Tamaso

Yasuo Namikawa

Kazushi Sawada

Takashi Tsuno

Takahiro Kumamoto

Katsuya Yamanishi

Minoru Mizutani

Mitsutoshi Nakata

Suetsugu Kanai

Kotaro Tanimura

A redox flow battery system includes pumps, a pump control unit, an SQC measuring unit, and a terminal-voltage measuring unit. The pump control unit includes a reference-flow-rate acquiring unit which acquires a reference flow rate of the pumps corresponding to the state of charge of electrolytes; a terminal-voltage determination unit which determines whether or not a terminal voltage of a battery cell reaches the lower limit or the ripper limit of a predetermined voltage range; and a pump-flow-rate setting unit which sets the reference flow rate for the pumps in the case where the terminal voltage does not reach the upper or lower limit of the predetermined voltage range, and sets a flow rate obtained by adding a predetermined flow rate to the reference flow rate for the pumps in the ease where the terminal voltage reaches the upper or lower limit of the predetermined voltage range.

Redox flow battery system, pump control unit, and method for operating redox flow battery

A power conversion apparatusaccording to an embodiment of the present invention includes a high-voltage side input terminal Tand a low-voltage side input terminal T, first and second output terminals Tand T, a power conversion circuitthat converts direct-current power input between the high-voltage side input terminal Tand the low-voltage side input terminal Tto generate alternating-current power between the first and second output terminals Tand T, and an inverted-voltage generation circuitthat generates an inverted voltage of a common mode voltage generated between the first and second output terminals Tand Tand inputs the inverted voltage to the low-voltage side input terminal T.

Power conversion apparatus with an inverted-voltage generation circuit

A power inverter circuitis a bridge power inverter circuit comprising first and second switching elementssequentially connected in series between input terminals on higher and lower voltage sides and third and fourth switching elementssequentially connected in series between the input terminals on the higher and lower voltage sides and alternately turning on a set of the first and fourth switching elementsand a set of the second and third switching elementsso as to convert a DC power fed between the input terminals on the higher and lower voltage sides into an AC power. One of the sets of the first and third switching elementsand the second and fourth switching elementsis subjected to switching control at a frequency higher than that of the other.

Power inverter circuit having switching elements

The stacked battery includes a negative electrode () and a positive electrode (). The negative electrode has a negative electrode main portion () and a negative electrode lead (). The positive electrode has a positive electrode main portion () and a positive electrode lead (). The negative electrode main portion and the positive electrode main portion are stacked in a thickness direction with the negative electrode lead and the positive electrode lead extending in different directions as viewed from above. The positive electrode lead is fixed to a positive electrode case. In the positive electrode lead, a break place (X) is provided outside the negative electrode main portion as viewed from above when the negative electrode and the positive electrode are placed on top of each other. The break place (X) is broken when a shock is applied to the electrodes.

Stacked battery with electrode having break portion

Provided is a transistor protection circuit capable of appropriately protecting a transistor even when a switching frequency is high. A transistor protection circuit according to an embodiment of the present invention is a transistor protection circuit for protecting a voltage-driven transistor that is switch-controlled by the application of a high-potential-side voltage or low-potential-side voltage of a power supply to a gate terminal of the transistor by a drive circuit. The transistor protection circuit has a power supply controller that gradually lowers the high-potential-side voltage of the power supply upon receiving a protection command for executing protection of the transistor.

Transistor protection circuit

A switching circuitcomprises a connection circuit cascade-connecting control terminals for controlling switching of n number of transistors M-Mn via n&#x2212;1 number of coils Lrespectively (n is an integer equal to or more than 2; and coils Lrespectively connected between one end of each of the transistors M-Mn and other end of a coil L, one end of the coil Lbeing electrically connected to a DC power source. The transistors M-Mn is sequentially switched with PWM signals inputted to an input terminal of the connection circuit. The switching circuitfurther comprises a transistor Minserted at the one end or the other end of the coil Lin cascade-connection.

Switching circuit and envelope signal amplifier

A switching circuit according to one embodiment has: N switching elements; a connection circuit including N&#x2212;1 first inductance elements that are connected in series; a second inductance element; and N third inductance elements. Control terminals of the N switching elements are connected to ends of the connection circuit and connection contacts, respectively. One end of the second inductance element is connected to a power supply. The N third inductance elements electrically connects one ends of the N switching elements and the other end of the second inductance element with each other, respectively.

A switching circuit according to one embodiment includes first to fourth semiconductor switch elements. A pulse-like signal is applied to each input terminal of the switch elements such that when the first and fourth switch elements are in an ON (OFF) state, the remaining switch elements are in an OFF (ON) state. The switching circuit includes first and second capacitance elements. The first capacitance elements connected between an output terminal of the second semiconductor switch element and the second capacitance elements connected between an input terminal of the second semiconductor switch element and an output terminal of the fourth semiconductor switch element has a capacitance to reduce a parasitic capacitance between the input and output terminals of each of the fourth and second switch elements at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

Switching circuit

A switching circuit according to one embodiment is a switching circuit including at least one semiconductor switch element having an input, output, and a common terminals, a pulse-like signal being applied between the input and common terminals to switch a current between the output and common terminals. The switching circuit further includes a capacitance suppression element section connected at least one of between the input and output terminals, between the input terminal common terminals, and between the output and common terminals. The capacitance suppression element section reduces a parasitic capacitance between the terminals of the semiconductor switch element where the capacitance suppression element section is connected to less than that obtained when the capacitance suppression element section is not connected at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse-like signal.

The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafermade of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer. In the activation annealing step, the waferis heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece, which is a generating source other than the wafer

Method of producing semiconductor device and semiconductor device

A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w) in the direction along the upper surface greater than a width (w) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

Semiconductor device and method for manufacturing the same

A lateral field-effect transistor capable of improving switching speed and reducing operationally defective products is provided. A gate wiring has a base, a plurality of fingers protruding from the base, and a connection connecting tips of adjacent fingers. The finger of the gate wiring is arranged between the finger of a source wiring and the finger of a drain wiring. The base of the gate wiring is arranged between the base of the source wiring and the fingers of the drain wiring and intersects with the fingers of the source wiring, with an insulating film interposed between the base of the gate wiring and the fingers.

Field effect transistor

An ohmic electrode for SiC semiconductor that contains Si and Ni or an ohmic electrode for SiC semiconductor that further contains Au or Pt in addition to Si and Ni is provided. In addition, a method of manufacturing the ohmic electrode for SiC semiconductor, a semiconductor device including the ohmic electrode for SiC semiconductor, and a method of manufacturing the semiconductor device are provided.

Ohmic electrode for SiC semiconductor, method of manufacturing ohmic electrode for SiC semiconductor, semiconductor device, and method of manufacturing semiconductor device

A switching circuit according to one embodiment includes: a switching element that has a first terminal and a second terminal, and is driven by a pulse signal to switch a conduction state between the first and second terminals; a power source section that supplies a voltage to the first terminal; a load circuit that is connected in parallel with the power source section; a passive circuit section that is connected between a connection point between the power source section and the load circuit, and the first terminal, and suppresses a current flowing from the connection point to the switching element at a frequency N times (N is an integer of 1 or more) as high as a clock frequency of the pulse signal; and a resonant circuit section that is connected between the passive circuit section and the connection point, and resonates at the frequency of N times.

There is provided a method of manufacturing a silicon carbide semiconductor device including the steps of: in a semiconductor stacked substrate including a first conductivity type silicon carbide crystal substrate, a first conductivity type silicon carbide crystal layer, a second conductivity type silicon carbide crystal layer, and a first conductivity type semiconductor region, forming a trench extending through the first conductivity type semiconductor region and the second conductivity type silicon carbide crystal layer into the first conductivity type silicon carbide crystal layer defined as a bottom surface; forming a silicon film on at least a part of the trench; heating the semiconductor stacked substrate having the silicon film formed to a temperature that is not less than the melting temperature of the silicon film; removing the heated silicon film; forming a gate insulating film on a surface exposed after the silicon film is removed; and forming a gate electrode layer on a surface of the gate insulating film.

Growing community of inventors

Osaka, Japan

Kazuhiro Fujikawa