Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Kazuhiro Akimoto

Katsumi Ogiue

Satoru Isomura

Masami Usami

Takeo Uchiyama

Masanori Odaka

Kinya Mitsumoto

Nobuo Tamba

Masamori Kashiyama

Takayuki Uda

Masayuki Ohayashi

Hiroshi Murayama

Toshiro Hiramoto

Hitoshi Abe

Tasuku Tanaka

Hisashi Ishida

Yoshikuni Kobayashi

Jun Hirokawa

Keiichi Higeta

Masato Iwabuchi

Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.

Semiconductor integrated circuit device and methods for production

A semiconductor integrated circuit device has a circuit construction which is devised with an output circuit for feeding an output current to an operating supply voltage in response to an output signal of a current switch circuit responding to an input signal. A constant current element for producing the operating current of the current switch circuit is fed with a constant voltage through a resistance element. A capacitor is coupled between the input of the constant current element and the operating supply voltage so that it constructs a time constant circuit together with the resistance element. The time constant circuit has a time constant set longer than the period of the output signal of the output circuit.

ECL interface circuit

Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Semiconductor integrated circuit device with two variable delay lines in

Disclosed are a semiconductor integrated circuit device and methods for production thereof. An embodiment of the invention is a semiconductor chip that comprises fuses constituting part of redundancy circuits formed therein, the fuses being made of the same ingredients as those of a CCB bump substrate metal. The fuses are patterned simultaneously during the patterning of the CCB bump substrate metal. This involves forming the fuses using at least part of the ingredients of an electrode conductor pattern in the chip. The cutting regions of the fuses are made of only one of the metal layers constituting the substrate. The principal plane of the semiconductor chip has a fuse protective film formed over at least the cutting regions of the fuses for protection of the latter. In operation, a switch MOSFET under switching control of a redundancy signal is used to select one of two transmission paths, one carrying an address signal or a decode signal, the other carrying a reference voltage. This allows a faulty circuit to be replaced with the corresponding redundancy circuit.

A semiconductor integrated circuit device formed with a single semiconductor substrate has, in one embodiment, an input buffer for receiving an input signal, memory blocks each producing an output signal responsive to the input signal and an output data selecting circuit for selectively transferring an output of one or more of the memory blocks. The input buffer, memory blocks and output data selecting circuit are arranged on the single semiconductor substrate in an order of progress of signal processing operations to be performed in the semiconductor integrated circuit device.

Semiconductor integrated circuit device having various blocks

A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for forming an address signal for the memory section and address signal delivering means for delivering the address signal for the memory section to the decode means. The address signal delivered from the address signal delivering means is defined by complementary signals.

Semiconductor memory system for use in logic LSI's

Semiconductor device for a ram disposed on chip so as to minimize

A bipolar type RAM having latches which accept and hold address signals, input write data and a write enable signal supplied from outside of the corresponding RAM chip, in accordance with strobe signals, and a timing generator circuit which forms the strobe signals and a write pulse required for a write operation and satisfying predetermined timing conditions, on the basis of a chip select signal supplied from outside.

Semiconductor memory device having a timing generator circuit which

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Tokorozawa, Japan

Kazuhiro Akimoto