Fuji Electric Co., Ltd.

Shin-etsu Handotai Co., Ltd.

Denso Corporation

Toyota Jidosha Kabushiki Kaisha

Nippon Soken, Inc.

Fuji Electric Systems Co. Ltd.

Shih-etsu Handotal Co., Ltd.

Kazuhiko Yoshida

Tatsuhiko Fujihira

Shoichi Furuhata

Naoki Kumagai

Takeshi Ichimura

Motoi Kudoh

Hiroshi Takeno

Kazunori Oyabe

Shin Kiuchi

Yoshihiro Ikura

Yukio Yano

Shinichi Jimbo

Shigeyuki Takeuchi

Masao Matsumine

Naoki Yaezawa

Yuuichi Harada

Tatsuhiko Fijihira

Nobuhiko Noto

Keigo Mizutani

Kazuo Tojima

Masayoshi Iwase

Mitsutaka Katada

Hidetaka Hayashi

Taishi Wakabayashi

Osamu Ishikawa

Tetsuhiro Morimoto

Hiroshi Ohtsuki

Hiroyuki Takahashi

Miho Niitani

Toshikazu Imai

A method for manufacturing a bonded SOI wafer, the method using a silicon single crystal wafer having a resistivity of 100 &#x3a9;&#xb7;cm or more as the base wafer, and including steps of: forming an underlying insulator film on a bonding surface side of the base wafer; depositing a polycrystalline silicon layer on a surface of the underlying insulator film; polishing a surface of the polycrystalline silicon layer; modifying the polycrystalline silicon layer by performing ion implantation on the polished polycrystalline silicon layer to form a modified silicon layer; forming the insulator film on a bonding surface of the bond wafer; bonding the bond wafer and a surface of the modified silicon layer of the base wafer with the insulator film interposed therebetween; and thinning the bonded bond wafer to form an SOI layer. This provides a bonded SOI wafer excellent in harmonic wave characteristics.

Method for manufacturing bonded SOI wafer and bonded SOI wafer

Disclosed is a method of forming a thermal oxide film on a silicon single crystal wafer, which includes throwing the silicon single wafer into a heat treatment furnace; elevating temperature of the heat treatment furnace up to a temperature T1 where a thermal oxide film is formed to form a thermal oxide film having a thickness d1; subsequently lowering the temperature of the heat treatment furnace down to a temperature lower than the temperature T1; and thereafter elevating the temperature of the heat treatment furnace up to a temperature T2 higher than the temperature T1 to additionally form a thermal oxide film having a thickness d2 thicker than the thickness d1. Thus, there is provided a thermal oxide film formation method to suppress occurrence of slip dislocation and/or crack of the silicon single wafer during formation of the thermal oxide film.

Thermal oxide film formation method for silicon single crystal wafer

In a SOI structure semiconductor device using a SOI substrate, a lattice distortion layer is formed by implanting Ar ions into a silicon substrate as an active layer. The lattice distortion layer is capable of serving as a gettering site. The dose amount of Ar ions is adjusted in such a manner that tensile stress in the lattice distortion layer is equal to or greater than 11 MPa and equal to or less than 27 MPa. Thus, the lattice distortion layer can prevent occurrence of a leakage current while serving as the gettering site.

SOI (silicon on insulator) structure semiconductor device and method of manufacturing the same

The present invention is a method for producing an SOI wafer comprising at least a step of forming an ion-implanted damaged layer by ion-implanting a neutral element electrically inactive in silicon from one surface of the base wafer or the bond wafer, in which ion-implanting in the step of forming the ion-implanted damaged layer is performed at a dosage of 1&#xd7;10atoms/cmor more and less than 1&#xd7;10atoms/cm. As a result, there may be provided a method for producing an SOI wafer having sufficient gettering ability while the suppression of leak failure, degradation of oxide dielectric breakdown voltage or the like is provided.

Method for producing SOI wafer

The present invention relates to a method for evaluating the SOI wafer in a method for evaluating an SOI wafer in which a sheet resistance of a buried diffusion layer of an SOI wafer that has at least an SOI layer on an insulator layer and has a buried diffusion layer whose impurity concentration is higher than other region of the SOI layer in an interface area with the insulator layer of the SOI layer is evaluated, the method including the steps of measuring a sheet resistance of the whole SOI layer or the whole SOI wafer, and estimating the sheet resistance of the buried diffusion layer by assuming respective layers that compose the SOI wafer to be resistors connected in parallel and converting the measured result of the sheet resistance measurement. As a result of this, there is provided a method for evaluating the SOI wafer that can directly measure the SOI wafer itself to be the product to thereby evaluate the sheet resistance of the buried diffusion layer thereof, without fabricating a monitor wafer.

Method for evaluating SOI wafer

A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating circuit attenuates the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.

Composite integrated semiconductor device

The present invention relates to a method for producing an SOI wafer, having at least a step of a bonding heat treatment for increasing bonding strength by heat-treating a bonded wafer obtained by bonding a base wafer and a bond wafer, in which argon is ion-implanted from a surface of either the base wafer or the bond wafer at a dosage of 1&#xd7;10atoms/cmor more at least before the bonding step, the surface ion-implanted with argon is used as a bonding surface in the bonding step, and an increase rate of temperature to a treatment temperature of the bonding heat treatment is 5&#xb0; C./minute or higher. Thus the present invention provides a method for producing an SOI wafer facilitating the efficient production of an SOI wafer having in the neighborhood of a buried insulator layer thereof a polycrystalline silicon layer uniform in thickness introduced and having high gettering ability toward metal contaminations in the SOI layer by a simple and low-cost method.

A semiconductor device is configured to prevent destruction of elements and/or miss-operation of the circuit by parasitic effects produced by parasitic transistors when a MOSFET of a bridge circuit is formed on a single chip. A Schottky junction is formed by providing an anode electrode in an n well region where a source region, a drain region, and a p well region of a lateral MOSFET. A Schottky barrier diode constituting a majority carrier device is connected in parallel with a PN junction capable of being forward-biased so that the PN junction is not forward-biased so that minority carriers are not generated, and thereby suppressing parasitic effects.

High power semiconductor device having a schottky barrier diode

A composite integrated semiconductor device. In one embodiment, an input surge/noise absorbing circuit absorbs surge from an input signal, an attenuating/level-shifting circuit attenuates or level-shifts the input signal, and an electrical signal converting circuit converts the input signal to an output signal. The input surge/noise absorbing circuit, the attenuating or level-shifting circuit, and the electrical signal converting circuit together form a unit, and a plurality of these units are arranged in parallel in one semiconductor substrate to form the composite integrated semiconductor device, resulting in a reduction in the number of discrete components mounted on a printed circuit board.

A semiconductor device realizes a high electrostatic discharge withstanding capability and a high surge withstanding capability within the narrow chip area of a lateral MOSFET used in integrated intelligent switching devices, double-integration-type signal input and transfer IC's, and combined power IC's. The semiconductor device includes a vertical bipolar transistor in which a base is electrically connected to an emitter and a collector, and a lateral MOSFET including a drain electrode connected to a surface electrode. The vertical bipolar transistor absorbs electrostatic discharge or surge energy when a high electrostatic discharge voltage or a high surge voltage is applied and limits the electrostatic discharge voltage or the surge voltage to be lower than the breakdown voltage of the lateral MOSFET.

Semiconductor device having a lateral MOSFET and combined IC using the same

A hydrogen sensor which may be employed in an overcharge/overdischarge detector for a battery and a hydrogen leakage detector for a fuel cell is provided. The hydrogen sensor includes a sensor element and a diffused resistor member. The gas to be measured passes through the diffused resistor member and reaches the sensor element. The sensor element outputs a signal indicative of the concentration of hydrogen contained in the gas as a function of a decrease in concentration of oxygen contained in the gas arising from reaction of the hydrogen on the oxygen. The diffused resistor member is so designed that speeds of diffusion of the hydrogen and the oxygen when passing through the diffused resistor member are different from each other for increasing the sensitivity of measurement of the concentration of hydrogen.

Hydrogen sensor for use in battery overcharge/overdischarge detector and hydrogen leakage detector

High power semiconductor device having a Schottky barrier diode

A depletion type MOS semiconductor device is provided which includes a p well region formed in a surface layer of an n drift layer, an n emitter region formed in a surface layer of the p well region, an n depletion region formed in the surface layer of the p well region, to extend from the n emitter region to a surface layer of the n drift layer, a gate electrode layer formed on a gate insulating film, over the n depletion region, an emitter electrode formed in contact with surfaces of both of the n emitter region and the p well region, and a collector electrode formed on a rear surface of the n drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (g ) of the MOSFET or IGBT. Other examples of MOS power IC may include circuits suitable for high-speed turn-on or turn-off operations, and circuits for supplying power to an internal control circuit.

Depletion type MOS semiconductor device and MOS power IC

A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z ) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z ) formed in a surface layer of the semiconductor substrate, and a diode (Z ) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z ) in a reverse direction. The first and second branches are connected in parallel with each other.

Growing community of inventors

Nagano, Japan

Kazuhiko Yoshida