Matsushita Electric Industrial Co., Ltd.

Kazuhiko Tsuji

Seiji Yamaguchi

Eisuke Ichinohe

Shuichi Kameyama

Shozo Okada

Joji Katsura

Takashi Ohzone

Kazuhiro Kobushi

Shigetoshi Takayanagi

In a MOS type semiconductor device, a source region, a channel region and a drain region of a MOS type device are arranged on the same plane, while a gate electrode is also arranged on the same plane adjacent to the channel region. Another set of a source region, a channel region and a drain region may also be arranged on the same plane and the latter MOS device Is arranged to the gate electrode. This the of device may be constructed as a CMOS type device. In another type of semiconductor device, the above-mentioned type plane arrangement of the source, channel and drain regions are layered via an insulator layer, while a gate electrode is provided vertically so as to be adjacent to the two channel regions.

High density integrated semiconductor device and manufacturing method

In a MOS type semiconductor device, a source region, a channel region and a drain region of a MOS type device are arranged on the same plane, while a gate electrode is also arranged on the same plane adjacent to the channel region. Another set of a source region, a channel region, and a drain region may also be arranged on the same plane, and the latter MOS device is arranged adjacent to the gate electrode. This type of device may be constructed as a CMOS type device. In another type of semiconductor device, the above-mentioned type plane arrangement of the source, channel, and drain regions are layered via an insulator layer, while a gate electrode is provided vertically so as to be adjacent to the two channel regions.

Silicon on insulator field effect transistors

In a MOS type semiconductor device, a source region, a channel region and a drain region of a MOS type device are arranged on the same plane, while a gate electrode is also arranged on the same plane adjacent to the channel region. Another set of a source region, a channel region and a drain region may also be arranged on the same plane and the latter MOS device is arranged to the gate electrode. This type of device may be constructed as a CMOS type device. In another type of semiconductor device, the above-mentioned type plane arrangement of the source, channel and drain regions are layered via an insulator layer, while a gate electrode is provided vertically so as to be adjacent to the two channel regions.

Method of manufacturing a high density semiconductor device

In a CMOS semiconductor device, a first MOS type device comprising a first source region, a first channel region and a first drain region is arranged on a first plane. A second MOS type device, comprising a second source region, a second channel region and a second drain region is arranged on a second plane above the first MOS type device, with an insulator layer interposed between the two devices. A gate electrode is provided so as to be vertically adjacent to the first and second channel regions.

High density integrated semiconductor device

Disclosed is a method of fabricating a polycidegate in semiconductor device which has a step of forming a conductor film of polysilicon on a substrate, a step of forming an ion implanted layer by implanting nitrogen ions into the polysilicon conductor film, and a step of forming a low resistance conductor film of titanium on the non-monocyrstalline conductor film. When a field effect transistor is formed by this method, using titanium nitride and/or TiSi.sub.2 alloy of the polysilicon conductor and low resistance conductor of titanium by heat treatment as a gate electrode material, the thickness of the alloyed layer is uniform, and breakdown of the gate insulating film due to local diffusion of low resistance conductor is not induced. In other embodiments, oxygen ions and silicon ions are also employed to form thin layers of tunnel oxide and amorphous silicon, respectively.

Method of fabricating a polycidegate employing nitrogen/oxygen

Method for measuring power supply current, e.g., standby current of a random access memory in which, before starting measurement of the power supply current, data is read-out from memory cell of the random access memory and opposite data is written in the memory cell so that the random access memory enters into an unstabilized state. By use of this method, the measurement of the maximum power supply current can be conducted precisely.

Method for measuring a characteristic of semiconductor memory device

A CMOS integrated circuit includes a P-channel type MOS transistor which is formed on an N-type silicon substrate, an N-channel type MOS transistor which is formed on a P well formed in the substrate, and parasitic bipolar transistors which are electrically connected to each other to form a kind of thyristor structure. A power supply voltage is applied to a source electrode of the P-channel type MOS transistor through a part of the substrate which presents a resistance. The resistance is electrically connected to the parasitic bipolar transistor of the thyristor structure to thereby prevent the occurrence of a latch-up phenomenon in which a large current continuously flows through the parasitic bipolar transistors and may destroy the CMOS integrated circuit. Because of the prevention of the latch-up phenomenon, the CMOS integrated circuit is always maintained in good condition.

CMOS integrated circuit

A metallization or conductor or semiconductor layer formed over one major surface of a semiconductor wafer subjected to anodizing to form an anodized coating which has excellent adherence to the conductor or semiconductor layer and which is used as an etching mask when the conductor or semiconductor layer is etched.

Growing community of inventors

Nara, Japan

Kazuhiko Tsuji