Fujitsu Semiconductor Limited

Kazuhiko Shimabayashi

Kazuhiro Tashiro

Yuji Maruyama

Takayuki Nakashiro

Susumu Koshinuma

Shigeru Goto

Chiaki Mimura

Masayoshi Shirakawa

A transition delay test is conducted such that an internal circuit that is a test object circuit in a semiconductor device is divided into a plurality of circuit blocks and a determination test is conducted while changing concurrently operating circuit blocks, a power supply noise generated during conduction of the determination test is detected, a suitable circuit scale on which the transition delay test can be normally conducted without being affected by the influence of the power supply noise is determined based on the result of the determination test and the detected power supply noise, and clocks to be supplied to the circuit blocks are controlled based on the determination result to limit the number of the concurrently operating circuit blocks.

Semiconductor device test method and semiconductor device

A testing device of a semiconductor device includes a first board having a plurality of openings; a frame body provided in the openings, the frame body having a frame in which a plurality of probe needles is provided; and a plurality of second boards provided perpendicular to the first board in the periphery of the openings, the second boards being connected to the first board; wherein the probe needles pierce the frame so as to be connected to the second boards from the periphery of the frame body via the openings.

Testing device for testing a semiconductor device

Growing community of inventors

Yokohama, Japan

Kazuhiko Shimabayashi