Uniden Corporation

Lapis Semiconductor Co., Ltd.

Pacific Communications Research Corporation

Kazuhiko Seki

Masato Tanaka

Hideki Kato

Shuzo Kato

Tadayuki Hattori

Meizhong Wang

Yoshinori Shinohara

Takashi Taya

Hideki Hashimoto

Eiji Shinsho

Shinichi Yamazaki

Isao Okazaki

Hiep Van Pham

Yasuhiro Kurita

Takayoshi Kaneko

Hideaki Ugawa

The present invention aims to provide a reception frequency control circuit that is small in mounting area and unaffected by disturbance where an FSK-modulated signal is demodulated. In the reception frequency control circuit, a reception signal processing unit converts an FSK-modulated digital signal to an intermediate frequency when the FSK-modulated digital signal is received. Thereafter, a frequency voltage converting unit converts the intermediate signal to a voltage signal and outputs an output signal. At the same time, an analog frequency controlling unit detects a frequency deviation from the output signal by analog processing. A digital frequency controlling unit generates a reception frequency control signal for correcting the frequency and feeds back the same to the reception signal processing unit. Stable frequency control can be realized by performing reception frequency control by a combination of an analog circuit-digital circuit in this way.

Reception frequency control circuit

Provided is a device for improving voice signal in quality by discriminating a radio environment of a signal transmission path and detecting a click noise. The device for improving voice signal in quality calculates an average value for a short interval of a received ADPCM code, identifies from such average value the nature of a radio environment of a signal transmission path, and considers that a click noise is occurred when the average value exceeds a threshold value assigned radio environment. The present invention comprises a click noise detector () for outputting a click noise detecting signal, and a click noise suppressing circuit for suppressing the click noise by setting the velocity coefficient of an ADPCM decoder () as '0' for a frame in which a frame error detecting signal, which represents the detection of a frame error of the received ADPCM code, and a click noise detecting signal are both detected.

Device for improving voice signal in quality

Provided is a code correction circuit for presuming an error pattern of the received code when a received ADPCM code contains a click noise and correcting such error. A device for improving voice signal comprises a click noise detector () which judges that a received ADPCM code contains a click noise when a short interval average value of the absolute value of the received ADPCM code exceeds a predetermined value, and a code correction circuit () which presumes an error position of the bit of the received ADPCM code and corrects such error so as to minimize the variation in the short interval average value of the absolute value of the received ADPCM code when a transmission error is generated in the receiving ADPCM code judged to be containing a click noise.

A receiver is provided, whereby bit error rate can be improved, while achieving savings in power consumption. The receiver comprises: a quadrature detector,for converting an intermediate frequency signal obtained on the basis of a reception signal to a base band signal; a comparator,for converting the base band signal to binary form after it has passed through a first LPF,, which is an analogue filter; a second LPF (CIC filter),for transmitting frequency components of the approximate square wave output by comparator,which are odd factors of the fundamental frequency of the signal; and a sampler,and comparator,which decode the output signal from the second LPF,in accordance with a clock reproduced by a clock reproducing circuit,on the basis of this output signal.

Receiver and method for demodulating reception signals

This invention makes it possible to link separately employed pagers, PHS, and other data terminals with computer networks such as the Internet, and to schedule transfer of data to the data terminals. In a system for transferring message to pagers from user terminals connected to the Internet, a user terminal indicates to a transmission server the time for message transfer, and the transmission server, using a code conversion table, converts the message to the code adapted to the particular pager service provider and pager terminal, and transmits the message to the pager terminal at the indicated time.

Scheduled data Transmission system, scheduled data transmission method, and transmission server

A spread spectrum transmitter and receiver are provided wherein data can be accurately decoded by removing the effect of mutual interference of the quadrature component and in-phase component even when there is carrier frequency error. In a method of spread spectrum communication using a QPSK modulation system, there are provided: a demodulating circuit that receives and demodulates a signal transmitted with a prescribed time difference Td applied between the IQ components; correlators that find the mutual correlation of the IQ components and spreading code; a sampling circuit that samples their output signals; a phase calculator that calculates the phase from the ratio of the IQ components of these output signals; a differential decoding circuit that performs differential decoding on this output signal; an automatic frequency control circuit that corrects the frequency error of this output signal; a decoding circuit; and a clock recovery circuit.

Spread spectrum transmitter, spread spectrum receiver and spread

A radio communication system in which each frame having an imbalanced transmission speed is time-divided to a low speed transmission area and to a high speed transmission area according to a specified ratio in the time domain. An upload signal as a first-directional signal and a download signal as a second-directional signal are allocated to the low speed transmission area and to the high speed transmission area respectively. In a case where a high speed transmission request is issued from a personal station (PS) to a base station (BS), the order of the upload signal and that of the download signal is exchanged in the time domain within one frame, so that the download signal and the upload signal are allocated to the low speed transmission area and the high speed transmission area respectively.

Radio communication system

The present invention allows efficient data compression when the contents of the control fields of packets are the same. An identity flag is substituted for a control field when the control field of an already-transmitted packet signal is identical to the control field of a packet signal which is to be newly transmitted. When non-identical, a non-identity flag is inserted to the control field. Thus, by using a larger number of small data format when identical control fields are transmitted consecutively, the data length of the control fields can be shortened.

Transmitting device, receiving device, packet transmission system and

A data collection system in which, in communications between each of terminal units and a data collector through a power line, the data collector subjects a polling signal generated by a polling generating circuit to spread spectrum modulation by a spreading section, and superimposes the spread signal on the power line, while each of the terminal units subjects the incoming spread signal thereto superimposed on the power line to de-spread spectrum demodulation and recognizes it, and superimposes the data subjected to spread spectrum modulation on the power line after a certain period of time different from that in other terminal unit has passed. The data collector collects the data obtained by subjecting spread signals successively coming thereinto each by being superimposed on the power line to de-spread spectrum demodulation according to the polling.

Data collection system

In a case where error correction code interleaved in the transmitting side and deinterleaved in the receiving side is subjected to decoding processing, a control circuit determines whether a result of decoding for each word is acceptable or not according to decoding acceptable/unacceptable data for each word stored in a decoding acceptable/unacceptable data memory, and subjects a correction object word not decoded to redecoding processing by controlling an error position estimating circuit and correcting data for the correction object word with an estimated error locator based on error position data for a forward word as well as a backward word from the correction object word.

Decoding apparatus and decoding method

An object is to provide a digital quadrature detection circuit wherein, without making the circuit complicated and without lowering performance, the operating frequency can be lowered and power consumption can be reduced. There are provided: a quasi-synchronous detector that takes the exclusive logical sum of a binary-converted intermediate frequency signal and a carrier signal, sampling means that respectively sample the output of the quasi-synchronous detector at M phases (where M is an integer of 1 or more) for each symbol, a bit adder that generates an M-bit parallel signal from the output signals of these, and low-pass filters that extract the low frequency components from this output. Whereas conventionally a 100-times clock pulse was employed in order to obtain an M-bit parallel signal, in this case, a 20-times clock pulse is sufficient, due to the provision of five sampling means.

Digital quadrature detection circuit

Transmission mode selection is enabled, so communication reliability, transmission speed, and equipment utilization efficiency are all high. A first transmission system whereby spectrum spreading is accomplished with a spread code 1 and data is transmitted, and a second transmission system whereby data is transmitted with a spread code 2, are provided. In high-reliability transmission mode, identical data from a data buffer is transmitted through both the first and second transmission systems to achieve space diversity. In high-speed mode, data divided by a data division circuit is transmitted simultaneously through the first and second transmission systems, making possible efficient data transfer. Control information insertion circuits append transmission mode data to the transmitted data.

Growing community of inventors

Tokyo, Japan

Kazuhiko Seki