Hitachi, Ltd.

Texas Instruments Corporation

Other

Kazuhiko Saito

Yoshitaka Tadaki

Toshihiro Sekiguchi

Keizo Kawakita

Toshiyuki Kaeriyama

Songsu Cho

Michio Tanaka

Michio Nishimura

Katsuo Yuhara

Shinya Nishio

Hideo Aoki

Toshikazu Kumai

A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.

Method of manufacturing semiconductor integrated circuit devices having a memory device with a reduced bit line stray capacity and such semiconductor integrated circuit devices

In an embodiment of a method of manufacturing semiconductor integrated circuit devices according to the present invention, word lines are provided in a straight form, which serve as gate electrodes of two selecting MOSFETs formed symmetrical about a center portion of an active region surrounded by a LOCOS oxide film on a semiconductor substrate, and bit lines have straight segments and protruding segments. Each protruding segment is formed to protrude from the bit line and is connected through a first contact hole to a first semiconductor region formed at the center portion of the active region. The straight line segments and the protruding segments are formed separately by two separate exposure steps.

Method of manufacturing semiconductor integrated circuit devices using

Growing community of inventors

Dallas, TX, United States of America

Kazuhiko Saito