Hitachi, Ltd.

Kazuhiko Sagara

Tohru Nakamura

Yoichi Tamaki

Noriyuki Homma

Kazuo Nakazato

Takeo Shiba

Tokuo Kure

Tetsuya Hayashida

Toshihiko Takakura

Masaharu Kubo

Masao Kawamura

Akihisa Uchida

Shigeo Kuroda

Mikinori Kawaji

Motoaki Matsumoto

Kiyoshi Inoue

Shinichiro Kimura

Masaru Ohki

Eiji Takeda

Yasunari Obuchi

Hirohiko Sagawa

Yuji Toda

Masahiro Abe

Tomoko Sakiyama

Eiji Oohira

Kiyoo Itoh

Masao Kondo

Norio Hasegawa

Shoji Shukuri

Digh Hisamoto

Hirotaka Nishizawa

Kaoru Umemura

Goro Kitsukawa

Masaru Izawa

Yoshiki Kawajiri

Toshiki Sugawara

Eiichi Murakami

Yoshifumi Kawamoto

Shinichi Minami

Masataka Shirai

Shinji Okazaki

Masanobu Miyao

Toshio Katsuyama

Kazuhiko Hosomi

Hiroshi Kakibayashi

Taro Ogawa

Akitoshi Ishizaka

Noriyuki Honma

Dai Hisamoto

Kiyoji Ikeda

Toru Koga

Shuji Shukuri

A micro-spectroscopic measuring device having a structure in which a spectroscopic element made of an array of photonic crystals with defects, flow paths for introducing a sample, and light detecting elements with sensitivity to a band from near infrared to infrared are stacked.

Micro-spectroscopic measuring device and micro-chemical system

A sign language interpretation apparatus for performing sign language recognition and sign language generation generates easily read sign language computer graphics (CG) animation by preparing sign language word CG patterns on the basis of actual motion of the hand through the use of a glove type sensor to generate natural sign language CG animation, and by applying correction to the sign language word CG patterns. Further, in the sign language interpretation apparatus, results of translation of inputted sign language or voice language are confirmed and modified easily by the individual input persons, whereby results of translation of the inputted sign language or voice language are displayed in a combined form desired by the user to realize smooth communication. Also, candidates obtained as a result of translation are all displayed and can be selected easily by the input person with a device such as a mouse. Further, when a polysemous word is available, the word is displayed while being changed in its display form, and other expressions are confirmed and modified with the mouse.

Sign language generation apparatus and sign language translation

Disclosed is a semiconductor memory having a self-amplifying cell structure, using (1) a writing transistor and (2) a reading transistor with a floating gate as a charge storage node for each memory cell, and a method of fabricating the memory cell. The writing transistor and reading transistor are of opposite conductivity type to each other; for example, the writing transistor uses a P-channel MOS transistor and the reading transistor (having the floating gate) uses an N-channel MOS transistor. The floating gate of the reading transistor is connected to a single bit line through a source-drain path of the writing transistor, the source-drain path of the reading transistor is connected between the single bit line and a predetermined potential, and the gate electrodes of the writing and reading transistors are connected to a single word line. At least the reading transistor can be formed in a trench, and the word line can be formed overlying the writing transistor and the reading transistor in the trench. Also disclosed is a method of operating the memory cell, wherein the voltage applied to the word line, in a standby condition, is intermediate to the voltage applied to the word line during the writing operation and during the reading operation.

Semiconductor memory having writing and reading transistors, method of

A semiconductor memory device whose data hold condition is not affected due to degradation of transistor characteristics by minimizing leakage charges and the switching transistor size. The semiconductor memory device employs memory cell charge holding electrode that is insulated from the remaining memory cell structure, particularly the switching transistor source drain leakage path. The write element controls the tunneling of charge carriers through such insulator to the charge holding portion or capacitor electrode, for writing data. Particularly, the write element includes a PN junction for various advantages.

Capacitive memory having a PN junction writing and tunneling through an

A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

Process of manufacturing semiconductor integrated circuit device having

Sources and drains of MOS transistors are formed after the formation of an emitter of a bipolar transistor, whereby the sources and drains are made smaller in thickness than the emitter. Since the sources and drains are not subjected to a high-temperature heat treatment conducted in the formation of the emitter, there is no fear of increase in thickness of the sources and drains caused by the diffusion of impurities. There can be formed a BiCMOS having a high integration density and superior characteristics.

Method for manufacturing a BiCMOS semiconductor device

Process of manufacturing semiconductor integrated circuit device and

Polycrystalline silicon which is provided within a trench for isolating a plurality of bipolar transistors from each other is electrically connected to the collector of one of the bipolar transistor. Since the trench for isolation can also be used to lead out the collector electrode, the required area is minimized. Thus, the arrangement is effective in creasing the integration density.

Semiconductor device with buried side contact

A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

Radiation resistant bipolar memory

A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.

A semiconductor device includes a semiconductor layer provided above a pair of bipolar transistors formed in a surface region of a semiconductor body. Schottky barrier diodes and resistors are formed in the semiconductor layer. The pair of bipolar transistors, the Schottky barrier diodes and the resistors are electrically connected to constitute a bipolar memory. Since the Schottky barrier diodes and the resistors can be formed above the bipolar transistors, an area required for the memory cell can be made greatly small and the occurrence of an hindrance caused by .alpha. particles is minimal.

Semiconductor device

A semiconductor device wherein a layer doped with impurities is provided between a buried layer and an epitaxial layer, said layer doped with impurities having a conductivity of the type opposite to that of said buried layer and said epitaxial layer, a reversely biasing voltage is applied across the buried layer and the layer doped with impurities, and side surfaces of the epitaxial layer are surrounded by an insulator. This helps effectively prevent the element formed in the epitaxial layer from being affected by .alpha.-particles and greatly improve reliability of the semiconductor device.

Semiconductor IC with dual groove isolation

Growing community of inventors

Tokyo, Japan

Kazuhiko Sagara