Seiko Epson Corporation

Kazuhiko Okawa

Takayuki Saiki

Takashi Sakuda

Yasuhiro Oguchi

Yasuhisa Hirabayashi

Satoshi Ito

Kunio Watanabe

Masahiro Hayashi

Toshimichi Yamada

Hiroaki Nitta

Masami Hashimoto

Tatsuro Shinmitsu

Kazuhiro Matsumoto

Provided is a drive control device including: a first output node coupled to a gate node of a high-side transistor; a second output node coupled to a drive node; a first transistor provided between a first power supply node and the first output node; and a current limiting circuit and a second transistor provided in series between the first output node and the second output node, in which the current limiting circuit limits a current from the drive node toward the first output node to a predetermined value. The current limiting circuit is, for example, a transistor having a direction opposite to that of the second transistor.

Drive control device, drive circuit, and vehicle

A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.

Semiconductor device

Semiconductor device with electrostatic discharge protection

The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur. A semiconductor device is equipped with a semiconductor substrate, an element isolation region formed on the semiconductor substrate, a first impurity diffusion region that is formed in the semiconductor substrate and surrounds the element isolation region, a second impurity diffusion region that is formed in the semiconductor substrate, a first wiring electrode and a second wiring electrode that are electrically connected to the first impurity diffusion region on both sides of the element isolation region, an output terminal that outputs signals to outside, a wiring that electrically connects the first wiring electrode and the second wiring electrode to the output terminal, and a third wiring electrode and a fourth wiring electrode that are electrically connected to the second impurity diffusion region corresponding to the first and second wiring electrodes.

The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.

Semiconductor device for electrostatic protection

Embodiments include a driver circuit that is suitable to prevent a delay in responding to an input of a drive signal and a method for manufacturing the same. Three contact holes are provided for each of the transistors T-Tfor connecting the gate electrodes of the transistors to the signal lines L, L-Lthat are separated from the transistors T-Tby the dielectric layerAs a result, the time for an input signal to reach the entire area of the gate electrodes becomes shorter and a response to an input of a drive signal becomes faster.

Driver circuits and methods for manufacturing driver circuits

A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor. A fourth diffusion region which makes up a Schottky diode together with the silicide layer is further provided between the silicide layer and the third diffusion region.

Semiconductor device having electrostatic protection circuit and method of fabricating the same

An electrostatic protection circuit of the present invention comprises: a first power supply terminal to which a first voltage is applied; a second power supply terminal to which a second voltage lower than the first voltage is applied; a first diode connected in a reverse direction between the first and second power supply terminals; and a second diode connected in a forward direction between the first and second power supply terminals. This configuration ensures that either one of the first and second diodes always operates in a forward direction to the static electricity applied between the first and second power supply terminals regardless of the polarity of the static electricity. Electrostatic charges therefore can be quickly absorbed through the diode in a forward direction.

Electrostatic protection circuit and semiconductor integrated circuit using the same

A semiconductor device is provided with an electrostatic protection circuit that causes rapid breakdown of a Zener diode immediately after a static charge is applied, to discharge the static charge by a high-gain thyristor with good response characteristics, and that has a small surface area. When a static charge is applied, a Zener diode breaks down, which acts as a trigger to turn on a thyristor formed of an NPN bipolar transistor and a PNP bipolar transistor. The PNP bipolar transistor is formed of p-type, n-type, and p-type impurity diffusion regions formed in the thickness direction of the substrate and the Zener diode is formed of n-type and p-type impurity diffusion regions. An n-type impurity diffusion region is provided adjacent to a surface-layer p-type impurity diffusion region, and these p-type and n-type impurity diffusion regions are connected to a signal terminal through a silicide layer formed on the surfaces thereof.

Semiconductor device having electrostatic protection circuit

A semiconductor integrated device is provided which consists of a plurality of circuit blocks. Each circuit block is connected to a power supply terminal and a ground terminal. Signal interface sections connect signal circuits among the circuit blocks. A plurality of first diodes are serially connected to one another in a first direction between the ground terminal of a first one of the circuit blocks and the ground terminal of another of the circuit blocks. A plurality of second diodes are serially connected to one another in a second direction that is opposite to the first direction between the ground terminal of the first circuit block and the ground terminal of the another circuit block.

Semiconductor integrated device

Semiconductor apparatus and process for manufacturing the same

The semiconductor device has an insulated-gate field-effect transistor (MOS transistor), a bipolar transistor, and a Zener diode. The MOS transistor is formed in a well of a first conductive type (p-type) and has a gate insulation layer, a gate electrode, side wall insulation layers, and second conductive type (n-type) of source and drain regions. The bipolar transistor has the drain region as a collector region, the well as a base region, and an n-type impurity-diffusion layer isolated from the drain region as an emitter region. The Zener diode is formed by the junction of an n-type impurity-diffusion layer continuous with the drain region and a p-type impurity-diffusion layer. The source and drain regions have a silicide layer formed on the surface thereof. A protection layer is formed on the surface of the n-type impurity-diffusion layer of the Zener diode.

Semiconductor device and method of fabricating the same

A semiconductor device, including an electrostatic discharge protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer, includes an N-type MOS transistor having a first diffusion region on a semiconductor substrate. This N-type MOS transistor is isolated from another MOS transistor by a first element isolation region. A second diffusion region is formed between the first diffusion region and first element isolation region. The first and second diffusion regions are separated by a second element isolation region. A silicide is formed on the surface of the semiconductor substrate excluding the first and second element isolation regions. A pad is connected to the second N-type diffusion region through a contact. An electrostatic charge injection through the pad and contact is discharged mainly through a first discharge path guided to a channel (P-type well) of the N-type MOS transistor through the second diffusion region (N-type), N-type well under the second element isolation region, and second diffusion region (N-type). A discharge path passing through the silicide layer rarely functions as a discharge path, since the contact resistance value between the silicide layer and first diffusion region is greater than the resistance value of the first diffusion region.

Semiconductor device having electrostatic discharge protection circuit

An object is to realize a protection circuit for protecting a semiconductor device from an ESD or other surge, said protection circuit having its improved reliability with a reduced scale of circuit. An n-type diffusion region (second diffusion region) is formed on a p-type well. A diode D1 formed by the n-type diffusion region and p-type well is connected to the gate electrode of n-type transistor. Thus, the potential difference between a channel region and the gate electrode is reduced to protect the gate oxide film. The n-type diffusion region is formed in the region of the gate electrode on the side of a source region between the source region and a p-type diffusion region (second diffusion region). The layout is determined such that a bipolar formed by the drain region, p-type well and n-type diffusion region will not be turned on. A single contact of minimum size is formed in the n-type diffusion region. When it is desired to form a silicide film, it may not overlap a device isolation film. The present invention may be applied to an output buffer, input buffer, input/output buffer, interface circuit between circuits operable in different power-supply systems or the like.

Protection circuit for semiconductor devices

In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its associated power branch-off member and the respective power line.

Growing community of inventors

Chino, Japan

Kazuhiko Okawa