Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Kazuhiko Okada

Tomohiro Fukuoka

Masaki Okada

Hiromi Yokoi

Nobuyuki Hattori

A processor includes a programmable logic circuit provided with a plurality of processing units. The programmable logic circuit is capable of reconfiguring a first logic circuit corresponding to first circuit configuration information according to a first process and a second logic circuit corresponding to second circuit configuration information according to a second process. Each of the first and second logic circuits includes an information holding unit. A first control circuit stores the second circuit configuration information in the information holding unit of the first logic circuit and generates an execution control signal for executing the first process. A second control circuit obtains the second circuit configuration information from the information holding unit of the first logic circuit in response to completion of the first process and controls the programmable logic circuit so as to reconfigure the second logic circuit corresponding to the second circuit configuration information.

Processor and control method for processor

A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination.

Circuit and method for dynamically changing reference value for address counter based on cache determination

A memory access determination circuit includes a counter that outputs a first value counted by using a first reference value, and a control unit that makes a cache determination of an address corresponding to an output of the counter, wherein, when a cache miss occurs for the address, the counter outputs a second value by using a second reference value.

Memory access determination circuit, memory access determination method and electronic device

Provided are an image display system and a control method for the image display system capable of displaying an image, which is represented by raster image data to be transferred through burst transmission and which is formed with a plurality of scanning lines, through simple control. An image display system includes a plurality of FIFO memories numbering the same as scanning lines in which pixels to be transferred during one burst transmission are contained do, and an input control unit that selects one of the plurality of FIFO memories according to a line number assigned to a line of pixels corresponding to unit transfer data, and stores second raster image data in the selected FIFO memory.

Image display system and control method therefor

A method and circuit for suppressing the generation of unnatural vertical streaks in output image data. A detection processing circuit generates a first noise correction value based on first and second noise detection signals from an OB region. A correction processing circuit performs an offset process on a first noise correction value to generate a second noise correction value and performs an FIR filter process on the second noise correction value to generate a noise correction signal NC. The correction processing circuit then corrects the effective image signal from the effective image region using the noise correction signal and performs a horizontal LPF process on the corrected effective image signal to generate output image data.

Image processing method and image processing circuit

The present invention relates to an image recorder including a selector circuit. Image data output from the image recorder, or output data of an encoder, is format converted in a format conversion circuit, and provided to a selector circuit arranged in a stage either preceding or following a pre-process circuit. The selector circuit selects one of input data from a CCD and input data from the format conversion circuit and provides the selected input data to the pre-process circuit. The output data of the encoder is then fed back. This configures a pseudo imaging system.

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Kasugai, Japan

Kazuhiko Okada