Seiko Epson Corporation

Kazuhiko Ohkawa

Takashi Sakuda

Yasuhiro Oguchi

Yasuhisa Hirabayashi

A semiconductor device assembly composed of a plurality of unit semiconductor devices formed into a logic circuit by selective connection among elements in the unit devices and among the unit devices. Each of the unit devices includes at least a first insulated-gate type field-effect transistor of a first conductivity type and a second insulated-gate type field-effect transistor of a second conductivity type which is disposed adjacent to the first transistor and has a gate electrode separated from a gate electrode of the first transistor. The gate electrodes of the respective transistors have at least a gate terminal portion at the side adjacent to each other, and the gate terminal portion of the first field-effect transistor has at least a first wire connecting location and a second wire connecting location. By using the second wire connecting location, wiring in and among the unit devices can be carried out via the shortest aluminum wires of a first layer, so that the wiring feasibility can be enhanced.

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Suwa, Japan

Kazuhiko Ohkawa