Kabushiki Kaisha Toshiba

Kazuhiko Ide

Sadao Tanikoshi

Kyosuke Dobashi

Takashi Yano

Yoshio Inagaki

Mitsuru Sugawara

Tomoaki Sugiyama

Masayuki Takami

Katsumi Kusama

Nobutaka Shinohara

Mototaka Kitajima

Mitsuru Otani

Takako Mori

Takashi Cho

Optical signals inputted to input ports are split in half by 1&#xd7;2 optical splitters respectively and the resulting signals are inputted to the input terminals of an optical matrix switch. The optical matrix switch switches between the routes of the individual optical signals and outputs the signal at any of the output ports. This enables the optical signal from the same input port to be outputted at two different output ports, which makes it possible to effect 'bridge' at the time of protection switching.

Optical switching apparatus and optical transmission apparatus

A serial transmission path switching system includes a matrix switch section for switching N&#xd7;M lines at a fixed rate. An optical receiving section is connected to receive an optical signal from an optical transmission path, photoelectrically convert it, and supply it to the matrix switch section. An optical transmitting section is connected to convert an output from the matrix switch section into an optical signal and send it to an optical transmission path. An input buffer is connected to the terminal of the optical transmission path connected to the optical receiving section to equalize the input signal from an input-side communication device, convert the signal into an optical signal, and send it to the optical transmission path. An output buffer is connected to the terminal of the optical transmission path connected to the optical transmitting section to convert an optical signal from the optical transmitting section into an electrical signal, equalize it, and output it to an output-side communication device.

Serial transmission path switching system

A matrix switch comprises a matrix switch main body ( ), a preprocessing block ( ) provided on an input side of the matrix switch main body ( ), and a postprocessing block ( ) provided on an output side of the matrix switch main body ( ), wherein each of the preprocessing block ( ), the matrix switch main body ( ) and the postprocessing block ( ) comprises a circuit, which parallel-converts a line input with each setting bit width, performs a bit stream operation in the setting bit width, serially converts it, and performs line output, respectively, and the matrix switch main body ( ) is divided into the setting bit width parallel-converted with the preprocessing block ( ) and switching-control is performed.

Matrix switch

In a memory device according to the present invention, an address for writing input data into a memory (306) is designated by a first address counter (303) which operates in response to a first clock, an address for reading written data from the memory (306) is designated by a second address counter which operates in response to a second clock, and a phase difference between the outputs of the individual address counter means (303, 313) is detected by a phase comparing section (307). A timing generating section (114-116) delays a signal acquired from the first or second clock to generate three or more timings, a time difference between any two of the timings being a any non-integer multiple of the first or second clock cycle. Further, a phase comparison discriminating section (120-122, 126) latches the output of the phase comparing section (307) at three or more timings, and outputs a signal for controlling a second address counter section (313) by majority decision on the latching result.

Memory device

A time-division multiplexing apparatus time-division multiplexes, in units of m bits, each bit of n-channel digital signals (n is a natural number more than 2), transmitted in a serial manner in synchronous to transmission clock pulses of a frequency of f0, by using m channels (m is a natural number smaller than n). Serial signals supplied to n channels are respectively converted into m-bit signals by shift register blocks provided for the n channels. The same bit outputs of the blocks are supplied, as an n-bit signal, to corresponding one of latch blocks, and are latched in synchronous to latch pulses of a frequency of 1/m of f0. The outputs of the latch blocks are input to n : 1 selector blocks. One of the bit signals of the selector blocks is selectively output in accordance with gate pulses.

Time-division multiplexing apparatus

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Yamato, Japan

Kazuhiko Ide