Canon Kabushiki Kaisha

Kazuhiko Haruma

Shinichi Yamashita

Koji Takahashi

Kenji Kawai

Nobutoshi Takayama

Taizou Hori

Nobukuni Roppongi

Takemi Tanno

A signal processor comprises a plurality of processing circuits for carrying out various kinds of processing which differ from one another; a memory circuit provided commonly for respective processing circuits, and a control circuit for carrying out access control between the respective processing circuits and the memory circuit, characterized in that the control circuit carries out address control in different units in accordance with the respective processing circuits.

Signal processor with a plurality of kinds of processors and a shared memory accessed through a versatile control means

Signal processor with a plurality of kinds of processors and a shared memory accessed through a versatile control unit

A signal processor comprises a plurality of processing circuits for carrying out various kinds of processing which differ from one another; a memory circuit provided commonly for respective processing circuits, and a control circuit for carrying out access control between the respective processing circuits and the memory circuit, characterized in that the control circuit carries out address control in different units in accordance with the respective processing circuits. Alternatively, the address control can reflect the different processing priority of different types of data. The processing circuits may be image data I/O means, audio data processing means, encoding/decoding means, error correction means and encoded data I/O means.

A picture coding apparatus includes a first compressing device for offset sampling input signals, and a second compressing device, having at an orthogonal transform circuit and a quantization device, for compressing the output from the first compressing device, wherein the quantization levels of the quantization device are set so that high-frequency components along a predetermined direction are quantized precisely on the basis of the visibility of each frequency component discriminated by orthogonal transform on a display screen.

Picture coding apparatus using orthogonal transforms

An image reproducing apparatus has a detection circuit for detecting a component difference between groups of encoded image data, a decode circuit for decoding the image data, a regulation circuit for regulating a component of the image data, and a control circuit for controlling the regulation circuit on the basis of a result of detection made by the detection circuit.

Image reproducing apparatus and image reproducing method

A reproducing apparatus is arranged to reproduce data, which are recorded in the form of predetermined blocks on a track formed on a recording medium, by causing a reproducing head to trace the track while moving the recording medium, write the reproduced data into a memory circuit, and rearrange the written data on the basis of an address assigned to each of the blocks and contained in the written data, thereby restoring the written data to the original recorded data. The memory circuit has memory capacities respectively assigned to a plurality of blocks obtained by a trace of the reproducing head. The reproducing apparatus is provided with an adjustment circuit for adjusting the remaining memory capacity of each of the plurality of blocks in accordance with the state of storage of the data stored in the memory circuit.

Reproducing apparatus varying reproduction speed according to memory

An image reproduction apparatus has an detection circuit for detecting the phase difference between coded image data and a decoding circuit for decoding the image data. The apparatus also includes a specifying circuit for specifying the transmission timing of the image data and a control circuit for controlling the specifying circuit according to the detection result of the detection circuit.

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Tokyo, Japan

Kazuhiko Haruma