Ricoh Company, Ltd.

Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Mitsubishi Denki K.k.

Kazuhiko Hara

Shinichi Yamaura

Takao Katayama

Keiichi Yoshioka

Shigeo Ueguri

Akihiko Iwata

Yoshihiro Ueda

Tatsuki Okamoto

Yoichiro Tabata

Takashi Yasui

Kazuhiko Iwanaga

Hiroshi Takafuji

Hiroshi Itoh

Masanobu Fukushima

Tetsuo Moriguchi

Yoshibumi Minowa

Takayasu Hirai

Yohsuke Fukuda

Yoichi Hisamori

Yoshitaka Kotani

Hiroshi Masuda

Shin-ichi Yamaura

Keiji Nakamura

An SIMD type microprocessor is disclosed. The SIMD type microprocessor includes plural PEs (processor elements) each of which provides an ALU (arithmetic and logic unit) for lower-order bits, an ALU for upper-order bits, a control circuit for lower-order bits, a control circuit for upper-order bits, a range determining circuit for lower-order bits, and a range determining circuit for upper-order bits. The SIMD type microprocessor further includes a global processor, a range designation bus for lower-order bits which connects the global processor to the range determining circuit for lower-order bits, and a range designation bus for upper-order bits which connects the global processor to the range determining circuit for upper-order bits. The global processor instructs the range determining circuits to designate corresponding ranges to be operated on by the corresponding ALUs via the corresponding range designation buses so that the ALU for lower-order bits and the ALU for upper-order bits can be operated separately.

SIMD type microprocessor having processing elements that have plural determining units

A communications device includes a communications circuit, a memory, an identifier generator, and a latency controller. The communications circuit exchanges serial data with a host computer and a downstream device, and includes a first input, a first output, a second input, and a second output. The first input receives data from the host computer. The first output transmits data to the host computer. The second input receives data from the downstream device. The second output transmits data to the downstream device. The memory is accessible through the communications circuit. The identifier generator generates an identifier number unique to the communications device in response to an identifier setup request received at the first input. The latency controller determines, based on the generated identifier number, a period of latency required to access the memory through the communications circuit.

System and method for serial data communications between host and communications devices, and communications device employed in the system and method

A reactor apparatus for a railway vehicle includes a coil assembly, a side cover, through bolts inserted into the coil assembly, cover supporting members, a pair of frames, and ribs that reinforce the pair of frames. A support/fixation section of each frame is fixed to an under surface of a vehicle pedestal. The pair of the frames are disposed on both sides of the coil assembly, and support the through bolts and the cover supporting member. For each rib, leg members that extend from corresponding reinforcing body are penetrated into and welded to the corresponding frame. For each cover supporting member, a leg member that extends from corresponding cover supporting body is penetrated into and welded to the corresponding frame.

Reactor apparatus for a railway vehicle

A parallel processor includes a global processor which interprets a program and controls the entirety of the parallel processor. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processing a plurality of sets of data. The global processor outputs a control signal to the plurality of processor elements, and, thereby, sets processor-element numbers corresponding to the plurality of processor elements as input values of the operation arrays, respectively.

Parallel processor and image processing apparatus adapted for nonlinear processing through selection via processor element numbers

A SIMD processor includes plural processor elements (PEs) each having a processing unit for data processing, a register for holding data to be processed or already processed by the processing unit, a data transfer bus interconnecting with other PEs, and a register controller for inputting a read or write signal to the register. Read and write processing steps in the processor are carried out by the register controller in response to the signals which are sent form the register controller and inputted into a register of specific processor elements responding to an addressing signal from an external interface. The processor is capable of transferring data directly to a specific processor element, thereby achieving higher speeds of data transfer and resultant data processing and makes flexible use of registers to thereby attain efficient data processing utilizing arbitrary combinations of the register depending on bit width of the data.

Single instruction stream multiple data stream processor

A water vaporization type cooling apparatus for cooling a heat-generating unit comprises a container which is made of a good thermal conductive material and has an opening, a selective water vapor permeable membrane which is mounted to the container so as to cover the opening and forms a closed space cooperatively with the container, and water charged in the closed space. In the water vaporization type cooling apparatus, the container is thermally connected to the heat-generating unit and dehydrated air flows along the outer surface of the selective water vapor permeable membrane, whereby the heat-generating unit is cooled down.

Water vaporization type cooling apparatus for heat-generating unit

When data that does not fill a bit size (32 bits) of a first register is stored in the first register, 8-bit data is supplied from a second register or a first constant generator to unfilled higher 16 bit positions of the first register, and a second constant generator supplies 8-bit data to fill the remaining bit positions in the first register.

Central processing unit compatible with bank register CPU

A processor used in a synchronous data transfer system in which a processor, a direct memory access controller and peripheral devices are connected to a memory via the same bus, includes a detection circuit for detecting whether the processor uses the bus in a forthcoming cycle, and a control circuit having a first terminal for acknowledging a request signal from the direct memory access controller requesting a use of the bus, only when the detection circuit detects that the processor does not use the bus in the forthcoming cycle, wherein the control circuit discards a right to use the bus and outputs a response signal to the direct memory access controller indicating that the processor grants the right to use the bus to the direct memory access controller, when the request signal is acknowledged.

Data processor used in a data transfer system which includes a detection

A central processing unit includes an adder dedicated to address calculation provided separately from an ALU, a first address data route connected to a program counter and a stack pointer register, a second address data route connected to a prefetch que, a predecoder for determining whether an instruction to be executed calls for an addressing mode whereby a value in the program counter or the SP register is added to an immediate address in an instruction code. With this arrangement, if the addressing mode is called for, address calculation by the adder is performed concurrently with computation using an operand for another instruction, in accordance with a control signal output by the predecoder.

Central processing unit adapted for pipeline process

A microprocessor having an instruction prefetch function includes a storage circuit in which an instruction externally supplied to the microprocessor via an external interface is stored, a first latch circuit which latches a write address value of the storage circuit in response to an interrupt signal externally supplied to the microprocessor, and an internal interrupt signal outputting circuit which compares a read address value of the storage circuit indicating the instruction stored in the storage circuit with the write address value supplied from the first latch circuit and which generates the internal interrupt signal only when the read address value and the write address value coincide with each other. The microprocessor processes an interrupt process in response to the internal interrupt signal.

Microprocessor having function of prefetching instruction

First and second circuits store therein source and destination operand addressing information from an instruction code as input information of a main decoder, respectively. A third circuit stores therein information other than operand addressing information from the instruction code as input information of the main decoder. A predecoder analyzes the instruction code and controls states of the first, second and third circuits. A first selector determines which information is input to the main decoder, from the first circuit, the second circuit or the third circuit. A processing selecting circuit causes the first selector to select information for each instruction, in a basic sequence of the first circuit, the second circuit and then the third circuit. The processing selecting circuit controls the first selector so that, if a state of at least one of the first and second circuits indicates that `processing is not required`, the circuit of the state of the indication is not selected and a subsequent circuit is selected instead. The main decoder obtains the information from the first, second and third circuits and controls each component of the central processing unit.

Central processing unit with a selector that bypasses circuits where

Central processing unit

An integrated circuit has a central processing unit for executing programs. The integrated circuit includes a register set, provided in the central processing unit, for storing crate required for executing a program in the central processing unit; and a register-file RAM, coupled to the central processing unit, for storing at least the same data as that stored in the register set in the central processing unit, wherein data stored in the register-file RAM can be supplied to the register set in the central processing unit.

Integrated circuit comprising a central processing unit for executing a

A central processing unit includes an instruction register storing instruction codes, a timing control unit controlling timings of steps of execution of an instruction, an execution unit executing an operation on data and temporarily storing data, the execution unit having a program counter and a data bus, a decoder decoding instruction codes read from the instruction register and controlling the instruction register, the timing control unit and the execution unit, and a next enable unit receiving an indication signal indicating proceeding to a next instruction should be performed and controlling outputting of the indication signal to the instruction register and the timing control unit based on first and second signals. The first signal is supplied from the decoder and instructing data on the data bus to be input to the program counter. The second signal is supplied from the execution unit and indicating whether a counter value of the program counter is an odd number or an even number.

Central processing unit including inhibited branch area

A general-purpose register group circuit provided in a data processing system includes a plurality of register groups connected to a first bus and a second bus, data being written into the plurality of register groups via the first bus according to a first control signal and being read therefrom via the second bus according to a second control signal. An output register group is connected to the plurality of register groups via the first and second buses. The data read from the plurality of register groups is written into the output register group according to a third control signal, and data read from the output register group is sent to an inner bus of the data processing system according to a fourth control signal. Each of the plurality of register groups includes a plurality of unit registers, each of which registers includes a first part for setting the second bus to either a high-impedance state or a reference level according to data latched therein and the second control signal. The output register group includes a second part for driving the inner bus according to a state of the second bus.

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Hyogo, Japan

Kazuhiko Hara