Kabushiki Kaisha Toshiba

Kioxia Corporation

Kazuhide Yoneya

Masaru Koyanagi

Katsuki Matsudera

Toshiki Hisada

Kosuke Yanagidaira

Natsuki Kushiyama

Takahiko Hara

Kaoru Nakagawa

Katsuya Okumura

Koji Kato

Tsunetoshi Arikado

Hiroyuki Koinuma

Mariko Kaku

Manami Kudou

Kenji Tsuchiya

According to one embodiment, a semiconductor device includes a first element isolating area, a first element area surrounding the first element isolating area, a second element isolating area surrounding the first element area a first gate electrode provided on and across the first element isolating area, the first element area, and the second element isolating area, and a second gate electrode isolated from the first gate electrode and provided on and across the first element isolating area, the first element area, and the second element isolating area.

Semiconductor device

A nonvolatile semiconductor memory device in an embodiment includes a semiconductor layer, a memory cell array, word lines, bit lines, a source line, and a control circuit. The memory cell array has memory strings, each of the memory strings having memory cells. The word lines are connected to the control gates of the memory cells. The control circuit controls a voltage applied to the semiconductor layer, the control gates, the bit lines, and the source line. When executing a read operation, the control circuit begins application of a first voltage to the source line at a first time, the first voltage having a positive value. The control circuit begins application of a second voltage to unselected word lines at the first time or thereafter, the second voltage setting the memory cells to a conductive state regardless of retained data of the memory cells.

Nonvolatile semiconductor memory device

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array including regular memory cells and permanent memory cells and a control circuit. The regular memory cells are capable of switching between a first data storage state and a second data storage state. The permanent memory cells are fixed in a third data storage state that is read as the same logic level data as the first storage state. Data is stored in at least one of the regular memory cells and at least one of the permanent memory cells. The control circuit rewrites at least one of the regular memory cells from the second data storage state to the first data storage state at the time of data holding. The control circuit performs a reading operation after rewriting the regular memory cells from the first data storage state to the second data storage state.

A semiconductor memory includes a converter configured to convert each read-data of plural bits read from a memory core into serial data, respectively, in synchronization with a read clock to generate converted read-data. An output register holds the converted read-data in synchronization with the read clock. A selector selects one bit from each plural bits of the converted read-data, in accordance with a control data, and to supply the selected bit to the output register.

Semiconductor memory

A semiconductor device includes a plurality of cell arrays, a selection control circuit to generate and to output a selection control signal. An array selection circuit generates internal address signals on the basis of an external address signal and the selection control signal. The array selection circuit outputs the internal address signals to the plurality of cell arrays to select ones of the cell arrays. A sales method for selling semiconductor devices includes presenting function-related information and price-related information on partially good semiconductor devices to client terminals and prompting the client terminals to provide purchase/non-purchase information and determining the possibility of successful transactions on the basis of the purchase/non-purchase information. A sales system for selling semiconductor devices uses the sales method and a sales program product for causing a computer system to sell semiconductor devices using the sales method.

Semiconductor device, sales method for semiconductor device, sales system for semiconductor device and program product storing sales program for semiconductor device

An input/output circuit inputs/outputs serial data. A register section comprises a first and a second register. The first register converts the serial data into parallel data. The second register converts parallel data into serial data. A first control signals supply a conversion timing for each bit when the serial data are converted into the parallel data. A second control signals supply a conversion timing for each bit when the parallel data are converted into the serial data. The signal generating circuit controls a timing of rise or fall of the first control signals and sets which of the memory cells should store a value for each bit, of the serial data, and controls a timing of rise or fall of the second control signals and sets which number of value of the serial data should be the value for each bit, of the parallel data read from the memory cells.

Semiconductor memory device inputting/outputting data synchronously with clock signal

A semiconductor integrated circuit device including an integrated circuit portion, a fuse element block, and a data transfer selecting circuit. The fuse element block includes a programmable fuse element. The data transfer selecting circuit selects one of the transfer of data programmed in the fuse element to the integrated circuit portion, transfer of data input from outside to the integrated circuit portion, and transfer of data programmed in the fuse element to outside.

Semiconductor integrated circuit device and method of manufacturing thereof

A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.

Semiconductor memory device

A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

A semiconductor integrated circuit device, which enables impedance adjustment of a particular pad without affecting other pads or signal wirings or without the need for a design change in basic layout, has formed a number of elements and wirings on and in a silicon substrate and pads stacked thereon via an insulation film A particular pad is connected to a signal wiring formed in a bus line region and a capacitor-forming conductor behaving as an impedance adjusting conductor is formed to surround the pad A source line conductor is made in a space between the pad and the capacitor-forming conductor to encircle the capacitor-forming conductor Therefore, the pad capacitance can be increased by using the space around the pad other signal wirings and any others formed in the bus line region are not affected substantially. Since here is used the portion around the pad which is not used normally, the basic layout need not be changed.

Semiconductor integrated circuit device with pad impedance adjustment mechanism

A semiconductor integrated circuit device comprises an integrated circuit portion, a fuse element block, and a data transfer selecting circuit. The fuse element block includes a programmable fuse element. The data transfer selecting circuit selects one of the transfer of data programmed in the fuse element to the integrated circuit portion, transfer of data input from outside to the integrated circuit portion, and transfer of data programmed in the fuse element to outside.

An output buffer generates '1' or '0' data based on control signals VA and VB transferred from memory cells through a DQ gate in a DRAM. The output buffer has first and second discharge circuits, and a first output transistor (PMOS Transistor). The second discharge circuit stops discharging the gate of the first output transistor after the voltage on the gate drops below the threshold voltage of the first output transistor and the first output transistor turns ON. After this time, only the first discharge circuit discharges the gate of the first output transistor. Further, the output buffer has first and second precharge circuits, and a second output transistor (NMOS transistor). The second precharge circuit stops charging the gate of the second output transistor after the voltage on the gate increases above the threshold voltage of the second output transistor and the second output transistor turns ON. After this time, only the second discharge circuit continues charging the gate of the second output transistor.

Growing community of inventors

Sagamihara, Japan

Kazuhide Yoneya