Spansion LLC.

Fujitsu Corporation

Kazuhide Kurosaki

Masaru Yano

Mototada Sakashita

Tsutomu Nakai

Kazuhiro Kitazaki

Takao Akaogi

Kenji Arai

Shigekazu Yamada

Akira Okada

Yoshinori Okajima

Junji Tomita

Kazuki Yamauchi

Junya Kawamata

Hirokazu Nagashima

Kenichi Takehana

Takuo Ito

An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.

Semiconductor device and method of controlling the same

The present invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. The present invention also provides a method of controlling the semiconductor device.

A semiconductor device of the present invention includes a booster circuit that boosts a selected word line (WL) to a given voltage higher than a power supply voltage and a charge pump circuit that retains the boosted word line (WL) at the first given voltage. When the booster circuit boosts the word line, the voltage level is degraded as the time goes. However, it is possible to program the memory cell and read out thereof properly by retaining the voltage of the word line with the charge pump circuit.

Semiconductor device and method for boosting word line

A semiconductor device has a plurality of bit lines BL provided in a memory cell area, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.

Semiconductor device and controlling method for the same

A semiconductor device includes: a pump circuit that boosts an output node connected to a memory cell array; an oscillator that outputs a clock to the pump circuit; and a detection circuit that outputs an actuating signal to the oscillator. In this semiconductor device, the actuating signal actuates the oscillator when the voltage of the output node of the pump circuit is lower than a first reference voltage, and the actuating signal stops the oscillator when the voltage of the output node is higher than a second reference voltage. In accordance with the present invention, when the voltage of the output node of the pump circuit is higher than the target voltage, the oscillator is stopped, and so is the pump circuit. Thus, unnecessary charge flow to the ground can be prevented, and the power consumption of the booster circuit can be reduced.

Voltage boosting device and method for semiconductor device

A semiconductor device includes a program voltage supply circuit that supplies a drain of a memory cell with a program voltage, and a pull-down circuit that pulls down a potential of an output of the program voltage supply circuit in accordance with a current that flows in a data bus line connected to the memory cell. The semiconductor device may include a program voltage restrain circuit that restrains an intensity of supply of the program voltage by the program voltage supply circuit.

Semiconductor device and method for controlling the same

A semiconductor device is provided that can perform simultaneous writing of a large number of bits, without an increase in chip size. This semiconductor device includes: a write data bus via which data are written into memory cells; a read data bus via which the data are read from the memory cells; a first write amplifier that writes data into the memory cells via the read data bus at the time of high-speed writing; a second write amplifier that writes data into the memory cells via the write data bus at the time of high-speed writing; a first sense amplifier that reads verified data from the memory cells via the read data bus; and a second sense amplifier that reads verified data from the memory cells via the write data bus.

Semiconductor memory device using read data bus for writing data during high-speed writing

A semiconductor device includes a first cascode circuit having a first current mirror amplifying a reference current flowing through a data line of a reference cell, and a second current mirror generating a first potential from an amplified reference current; and a second cascode circuit having a third current mirror amplifying a core current flowing through a data line of a core cell, and a transistor receiving a gate voltage corresponding to the amplified reference current and generating a second potential based on a difference between an amplified core cell current and the amplified reference current. Since the second potential is generated by the difference between the core cell current and the reference cell current, the second potential swings in the full range of the ground power supply voltage to the ground potential, and the range of the amplitude of the power supply voltage can be efficiently utilized. Sensing is enabled for a fine current margin.

Semiconductor device and method of generating sense signal

The precharge circuit is provided for precharging, before programming the data, the voltage of the source line ARVSS commonly connected to the memory cells provided in the same sector. The voltage of the source line ARVSS of the memory cell MC is precharged before programming the data, and the voltage of the source line ARVSS of the memory cell MC is not lowered at the time of programming the data, even if the data programming period is shortened. It is thus possible to prevent the leak current during the programming and program the data into the memory cell MC optimally.

Semiconductor device and source voltage control method

A flash memory having a nonvolatile memory cell, includes a plurality of banks each having a plurality of sectors, an erasing voltage generator circuit and a writing voltage generator circuit, wherein while an applying an erase pulse to a sector to be erased in a first bank, an erasing control is performed by, a pre-writing control is concurrently performed by applying a writing pulse to a sector to be erased in a second bank. At the time when erasing control of the sector to be erased in a first bank is finished, pre-writing control of the sector to be erased in a second bank is finished or partially finished, and thus the time required for erasing operations of the first and the second bank can be reduced.

Flash memory with shortened erasing operation time

A semiconductor memory including an address change detection unit for detecting a change of an address and outputting an address change detection signal, a selection unit for selectively switching the polling data and the read data by a polling signal, and outputting its data to the output buffer, and a delay unit for inhibiting the polling signal from being transferred to the selection unit while the address change detection signal is activated. When the polling signal changes while a sense amplifier senses data, the logic level of a signal output from the output buffer is inhibited from being changed. This prevents any malfunction caused by output noise generated during the data sense operation of the sense amplifier.

Semiconductor memory and output signal control method and circuit in semiconductor memory

The non-volatile semiconductor memory of the present invention is comprised of: a memory cell array including a plurality of memory cells which is disposed at intersections of a plurality of bit lines and word lines and are connected to said bit lines; and a writing circuit which receives an address signal and supplies a bit line voltage to the bit line connected to the memory cell selected with the address signal during writing operation. The writing circuit changes, based on the address signal, a level of the bit line voltage depending on a position of the selected memory cell in the memory cell array. The writing circuit operates, based on the inputted writing address, to further increase a level of the bit line voltage supplied to the memory cell as the wiring distance via the bit line from the output end of the bit line voltage of the writing circuit thereto is longer, fluctuation of writing speed in each memory cell of a memory cell array is reduced.

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Tokyo, Japan

Kazuhide Kurosaki