Sony Corporation

Kazuhide Koyama

Hirofumi Sumi

Mitsuru Taguchi

Keiichi Maeda

Yukiyasu Sugano

Kazuhiro Hoshino

Toshiharu Suzuki

Shinji Minegishi

Tatsuji Oda

A memory device includes a plurality of memory elements, each having a first electrode, a second electrode, and a memory layer between the first electrode and the second electrode. The plurality of memory layers are in a dotlike pattern. Two adjacent first electrodes share a same memory layer.

Memory device and method of manufacturing the same

Disclosed is a method of manufacturing a semiconductor device. A plurality of device separation regions are formed in an SOI layer of an SOI substrate, a desired impurity is implanted into a body portion of an Si active layer region, and thereafter a gate electrode is formed with a gate insulation film therebetween. Thereafter, an impurity is implanted into the Si active layer region to form extension portions of source/drain portions, and then an impurity different in polarity from the impurity in the source/drain portions is halo-implanted to form a reverse-characteristic layer. In the halo implantation, the range of projection is set to reach the inside of a buried oxide film. With this configuration, in a fully depleted SOI-MOSFET or the like provided with a thin film SOI layer, it is made possible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance and to secure a sufficient driving capability.

Method of manufacturing semiconductor device

Disclosed is a method of manufacturing a semiconductor device. A plurality of device separation regions are formed in an SOI layer of an SOI substrate, a desired impurity is implanted into a body portion of an Si active layer region, and therereafter a gate electrode is formed with a gate insulation film therebetween. Thereafter, an impurity is implanted into the Si active layer region to form extension portions of source/drain portions, and then an impurity different in polarity from the impurity in the source/drain portions is halo-implanted to form a reverse-characteristic layer. In the halo implantation, the range of projection is set to reach the inside of a buried oxide film. With this configuration, in a fully depleted SOI-MOSFET or the like provided with a thin film SOI layer, it is made possible to simultaneously achieve an improvement of roll-off characteristic and a reduction in parasitic resistance and to secure a sufficient driving capability.

There is provided a semiconductor apparatus, and a fabrication method thereof, which are improved such that a reduction in concentration at the SOI active layer is prevented, and a parasitic MOSFET is not formed even in cases where Mesa-type isolation techniques and the STI isolation method are applied to form a MOSFET in an SOI layer. In an isolation step for separating and forming a plurality of device regions, a layered film of a nitride film (Si N ) and an oxide film (SiO ) is taken as an isolation mask, and a semiconductor layer (SOI layer) is removed from the isolation region by etching. Subsequently, a SiON film ( ) is formed on a sidewall surface of an SOI layer ( ) by a nitridation oxidation process. Thereafter, isolation is performed by the STI method. Finally, an oxide film ( ) and an electrode ( ) are formed, and a MOSFET is completed.

Semiconductor device and fabrication method therefor

A metallization method for filling an Al-based material in a contact hole having a barrier metal structure, in which high barrier characteristics and high step coverage may be achieved simultaneously, is proposed. The present invention is based on two concepts. The first concept is to provide a Ti/TiON/Ti three-layer barrier metal structure and to deposit a layer of the Al-based material by high temperature sputtering. Sufficient barrier characteristics may be provided by the intermediate TiON layer of the three-layer structure. The interface between the Al-based layer and the barrier metal layer is the Ti layer having excellent wetting characteristics with respect to the Al-based layer so that the contact hole can be filled uniformly without forming voids. The second concept is to set the substrate heating temperature during high temperature sputtering to 450 to 550&deg; C. and to set the deposition rate to 0.6 &mgr;m/minute or less. In this manner, moderate Al migration and sufficiently long reaction time may be assured even on a Ti layer which partially reflects the rough surface morphology of the TiON layer for further improving reliability in filling.

Aluminum metallization by a barrier metal process

A process of forming an interconnection of a semiconductor device, which is intended to prevent re-oxidation of a Si-rich layer formed on the surface of an insulating layer when the surface of the insulating layer is subjected to sputter-etch cleaning, whereby the degree of crystal orientation of an interconnection material layer formed on the insulating layer is improved. The process includes a first step of forming an insulating layer made of a silicon based material on a base body; a second step of sputter-etch cleaning the surface of the insulating layer; a third step of depositing an interconnection material layer on the insulating layer by sputtering; and a fourth step of patterning the interconnection material layer on the insulating layer, thereby forming an interconnection; wherein the sputter-etch cleaning in the second step is performed while the base body is cooled.

Process for forming interconnection of semiconductor device and

In a method for making a multilayer wiring structure, a second insulating film having an etching rate slower than a first insulating film is provided on the first insulating film covering a wiring pattern; an opening is formed in the second insulating film in a portion corresponding to a connecting hole to be formed afterwards; a third insulating film having an etching rate faster than the second insulating film is provided on the opening and the second insulating film; a groove is formed, so as to expose the opening, in the third insulating film in a portion where an upper-layer wiring pattern is formed, and the connecting hole reaching the wiring pattern is formed; and a connecting plug is formed by packing a conductive material in the connecting hole, and the upper-layer wiring pattern is formed by packing a conductive material in the groove.

Method for making multilayer wiring structure

A process for fabricating interconnection of a semiconductor device is provided which allows the physical vapor deposition and reflow treatment to be performed in different apparatuses and requires no surface treatment prior to the reflow treatment. The process comprises the steps of forming a metallic interconnection material layer on a substrate by means of physical vapor deposition using a metallic interconnection material; forming an oxidation preventive film on the metallic interconnection material layer; subjecting the metallic interconnection material layer to reflow treatment to form a complete solid solution of the components constituting the oxidation preventive film with those of the metallic interconnection material layer; and patterning the metallic interconnection material layer to form an interconnection.

Process for fabricating interconnection of semiconductor device

Disclosed is a semiconductor device having a structure in which even if a misalignment occurs an upper trench and a connection hole, that is, the upper trench is offset from the connection hole, it is possible to suppress a reduction in contact area between an interconnection material and a connection hole burying material and hence to reduce an increase in contact resistance, and which is particularly suitable for a borderless trench interconnection structure, and a method of fabricating the semiconductor device. The semiconductor device includes: a substrate; an interlayer insulating film formed on the substrate; a connection hole formed in the interlayer insulating film; a connection plug formed by burying the connection hole with a connection hole burying material; a trench formed in the interlayer insulating film; and a trench interconnection formed by burying the trench with an interconnection material. In such a semiconductor device, the connection plug enters in the trench interconnection in such a manner that at least part of a side surface of sid connection plug is brought in contact with the trench interconnection.

Semiconductor device with improved trench interconnected to connection

In a wiring system provided by the present invention, a first conductive wire is provided on a surface on one side of an dielectric layer of a semiconductor device, a second conductive wire made of an Al like metal is provided on a surface on the other side of the dielectric layer, a connection hole is drilled through the dielectric layer, the first and second conductive wires are connected to each other through the connection hole, and a compensation pattern made of the Al like metal is created in the second conductive wire, so that generation of voids in the Al like metal of the second conductive wire due to an electro-migration phenomenon is prevented, enhancing the reliability of the wire.

Aluminum like metal wiring for semiconductor devices

The present invention provides a process for fabricating a connection structure comprising a anti-reaction layer having excellent barrier properties and having improved ohmic characteristics with respect to the semiconductor substrate. Accordingly, the present invention comprises forming a first anti-reaction layer by temporarily ceasing the film deposition, and then initiating the film deposition again to form a second anti-reaction layer on the surface of the previously deposited first anti-reaction layer. A heat treatment can be applied to the structure after depositing a anti-reaction layer.

Process for fabricating connection structures

A metallization method for improving wettability and reactivity of a titanium (Ti) based barrier metal layer with respect to an aluminum (Al) based material and simultaneously achieving high barrier properties and superior step coverage, is proposed. An operation of increasing the crystal grain size of and planarizing at least a surface region of a barrier metal layer is effected simultaneously at the time of formation of a barrier metal layer. In this manner, Al migration characteristics and reactivity on a barrier metal surface are improved so that voids are not produced when an Al-based material layer is charged into small-sized connecting hole by a process sensitive to surface morphology, such as high temperature bias sputtering. By this technique, wettability of a material layer having distinctly inferior wettability with Al, while being excellent in barrier properties, such as a TiON layer, may be improved. As a smoothing operation, bias sputtering, laser irradiation and lamp annealing are proposed. Satisfactory results have been achieved on applying these to a Ti/TiON/Ti system, a Ti/TiON system or to a Ti/TiON/TiSi.sub.2 system.

Aluminum metallization method

A method of forming wirings which comprises depositing an Al or Al alloy wiring material to a predetermined thickness on a semiconductor substrate having a stepped dent such as a connection hole thereby filling and flattening the dent, then etching back the Al or Al alloy film to leave a portion to a predetermined thickness in the direction of the thickness, and a stop of patterning the thus left Al or Al alloy wiring material in desired wiring shape. Filling and flattening for the dent of the semiconductor substrate can be attained without causing trouble for the subsequent flattening of the inter-layer film, while preventing the reduction of the Al grain size of the Al or Al alloy film and preventing reduction of the electromigration resistance.

Growing community of inventors

Kanagawa, Japan

Kazuhide Koyama