Renesas Technology Corp.

Kazuhide Kawade

Takanobu Naruse

Hirokatsu Noguchi

Yoshiyuki Matsumoto

It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processorcomprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.

Growing community of inventors

Kiyosu, Japan

Kazuhide Kawade