Mitsubishi Denki Kabushiki Kaisha

Kazuharu Nishitani

Masao Takiguchi

Satoshi Matsumoto

Taiji Imazu

A semiconductor memory device includes a data line for receiving a voltage and an inverted data line having a voltage inverted relative to the voltage received by the data line; a first transistor and a second transistor for selecting a memory element for writing in data and reading out data through the data line and the inverted data line, respectively; two inverters, each inverter including a first p channel transistor and a first n channel transistor with the input and the output of the one inverter respectively connected to the output and the input of the other inverter and between either the source and the drain of the first transistor or the drain and the source of the second transistor; and a second p channel transistor connected in series to the first p channel transistor of one of the two inverters. When the same data, '0' or '1', is to be written into all memory elements, the second p channel transistor is turned off to inhibit 'H' driving of the inverters and no 'H' driven output of the inverter collides with the output of an 'L' driven writing driver. As a result, writing of the same data into all memory elements can be performed without malfunction.

Semiconductor memory device

In order to obtain an output circuit having pulldown resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an OR gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pulldown transistor (Q.sub.1) are connected to a second input end and an output end of the OR gate (G5) respectively. The pulldown transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.SS) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a high logical level, the pulldown transistor (Q.sub.1) is quickly driven by pulses generated by the pulse generation circuit (SG), to lower the potential of the input end of the inverter (11).

Pulldown resistance control input circuit and output circuit

In order to obtain an output circuit having pullup resistance which feeds no through current to a CMOS inverter even if output impedance of a front stage circuit is in an extremely high state, an input end and an output end of an inverter (G1) are connected to an input terminal (P.sub.i) and a first input end of an AND gate (G5) respectively. A pulse generation circuit (SG) and a gate of a pullup transistor (Q.sub.1) are connected to a second input end and an output end of the AND gate (G5) respectively. The pullup transistor (Q.sub.1) has a drain and a source which are connected to the input terminal (P.sub.i) and a power source (V.sub.DD) respectively. An input end of a CMOS inverter (11) is connected to the input terminal (P.sub.i). Even if the front stage output impedance is extremely increased after the potential of the input terminal (P.sub.i) has been at a low logical level, the pullup transistor (Q.sub.1) is quickly driven by pulses generated by the pulse generation circuit (SG), to increase the potential of the input end of the inverter (11).

Pullup resistance control input circuit and output circuit

A buffer 6 operating in response to an amplitude level of a clock signal is provided in a semiconductor integrated circuit device such as, a gate array. By selectively applying clock signals of different amplitude corresponding to operation modes, the buffer 6 operates selectively. Therefore, for example, the designation of a test mode can be detected by the buffer 6. As a result, it is not necessary to provide a terminal for externally receiving a test mode signal.

Semiconductor integrated circuit device responsive to clock signals

A reset circuit resets an internal circuit (3) included in an electronic apparatus. The internal circuit generates a pulse signal indicating that the internal circuit is in an enabled state. This pulse signal is supplied to an inverter (63) through an integrating circuit comprising a resistor (61) and a capacitor (62), so that the pulse signal in the inverter is inverted in polarity to be supplied to one input terminal of an AND gate as a reset inhibit signal. To the other input terminal of the AND gate is supplied a reset signal generated based on transient phenomena at the time of turning on of the DC power source. If the AND gate is closed by the reset inhibit signal, the internal circuit does not receive the reset signal from the AND gate. Accordingly, the internal circuit in operation will never be reset if the reset signal is supplied thereto.

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Itami, Japan

Kazuharu Nishitani