Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Kazufumi Tanoue

Hideyuki Kabuo

Ryutaro Yamanaka

Tomoko Chiba

Daisuke Takeuchi

When a barrel shift device is divided into pipeline registers and a shift process is executed in a multistage process stage, by decoding a second control signal for controlling a shift amount of a second shift circuitusing a decoding circuitit is detected at what digit positions in intermediate data in an intermediate data holding circuitdata elements which are to be finally output as output data from the second shift circuitare located. Based on a result of the detection of digit positions by the decoding circuitthe intermediate data holding circuitholds only data elements to be finally output, among data elements in the intermediate data, and does not hold unnecessary data elements which are not included in the output data. Therefore, by controlling a data storage operation in the intermediate data holding circuitan increase in power due to the pipeline structure is suppressed.

Barrel shift device

An interleaving/deinterleaving method and apparatus may interleave/deinterleave first data to produce second data so that the arrangement of data elements of the second data is different from that of the first data. To accomplish this, word data that are part of the first data are read from a data storage section and a data element to be processed is selected from the word data for output. The operations of reading word data and selecting data elements of the word data to output are repeated, and a sequence of data elements to be processed at the time of repetition is determined in accordance with the arrangement of the data elements of the second data.

Interleaving/deinterleaving method and apparatus

In a binary fixed-point number system in which the most significant bit is a sign bit and the decimal point is between the most significant bit and a bit which is lower by one bit than the most significant bit, the circuit scale for digit place aligning means is reduced and a double-precision multiplication with an excellent efficiency is realized. Products of the high-order word/low-order word of a double-precision multiplicand and the high-order word/low-order word of a double-precision multiplier are obtained by using a single-precision multiplying device. A digit place alignment addition operation is performed on the obtained products to produce a double-precision multiplication result. In this case, at least two digits are set before the decimal point, thereby allowing each of the products of the high-order word/low-order word of the double-precision multiplicand and the high-order word/low-order word of the double-precision multiplier, to be obtained at a bit width which is larger by at least one bit than a bit width of double precision.

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Osaka, Japan

Kazufumi Tanoue