Fujitsu Corporation

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Kazufumi Komura

Yoshiharu Kato

Satoru Kawamoto

Masami Nakashima

Takayoshi Nakamura

Keiichi Fujimura

Keigo Nakashima

Masahito Hirose

Masaki Nagato

Takaaki Furuyama

Shigetaka Asano

Tohru Yasuda

Nobuyoshi Nakaya

Katsumi Furukawa

Kanta Yamamoto

Hirohisa Nishiyama

A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

Semiconductor device and operation monitoring method for semiconductor device

The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.

Semiconductor memory device, refresh control method thereof, and test method thereof

A capacitance cellis wired while using adjacent wiring layers Ma and Mb as a pair of electrode layers Tand Torthogonally to opposed lateral end faces out of lateral end faces X, X, Y, and Ythat section the cell in a plane direction. Contact surfaces of electrode surfaces Tand Twith the lateral end faces are second connection terminals Tand T. For longitudinal pathways, first and second via contact layers Vand Vare connected. The first via contact layer Vinterconnects the wiring layers Ma and Mb. The second via contact layer Vis connected to a wiring layer located outside beyond an upper or lower end face Z, Z. The second via contact layer Vis connected to a first connection terminal T, Tlocated on the upper or lower end faces Z, Z. The capacitance cellsare linked via the first and second connection terminals so that a capacitance element having a free shape is formed. A capacitance cell, a semiconductor device, and a capacitance element arranging method that allow to arrange capacitance elements each using wiring layers sandwiching an interlayer insulating film with less of a leak current as electrode layers according to the shapes of unused areas.

Capacitance cell, semiconductor device, and capacitance cell arranging method

A semiconductor integrated circuit device provided with a plurality of power supply wire layers including a first potential power supply wire and a second potential power supply wire formed in different layers. At least one capacitor contact wire extends from one of the first and second potential power supply wires toward the other one of the first and second potential power supply wires so as to form a capacitor between each capacitor contact wire and its surrounding wires.

Semiconductor integrated circuit device

An interface test can be performed by, for example, only a self apparatus when interface operation specifications are different between the self apparatus and an original connection partner apparatus. An LSI has a plurality of interfaces (IFs) for transmission/reception of data with an external device, and the LSI includes an emulation control unit for allowing one of the two of the plurality of IFs to perform an operation of emulating an IF of a connection partner device having operation specifications different from those of the LSI, when two IFs are connected to each other via a transmission line.

Semiconductor integrated circuit apparatus and interface test method

It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k&#x2212;1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

Semiconductor memory device and method of controlling the semiconductor memory device

A power consumption reduction circuit for reducing power consumed by a clock tree network including a transmission control circuit. The power consumption reduction circuit includes a transmission control circuit for controlling transmission of the clock signal to the buffer circuit group so as to selectively provide and interrupt the clock signal. A switch circuit disconnects the buffer circuit group from a power supply when the transmission control circuit interrupts the clock signal.

Power consumption reduction circuit for clock network

A shift redundancy circuit for enabling switching operation of memory blocks to be executed at a high speed and for reducing current consumption relating to the switching operation. A shift control circuit includes a first shift control circuit for generating a first shift signal corresponding to a first deficiency address of a memory block and a second shift control circuit for generating a second shift signal corresponding to a second deficiency address of a memory block. When the memory blocks are switched, a shift signal controlling the switching of selection line switches are selected from the first shift signal whose state is determined in advance, the second shift signal whose state is determined in advance, and a low potential power supply.

Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device

A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k&#x2212;1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines.

A semiconductor device capable of detecting and suppressing SSO noise after the semiconductor device has been mounted on a board. The semiconductor device includes an output circuit for outputting parallel output signals in accordance with a clock signal, an SSO noise generation circuit for activating the output circuit to generate SSO noise, and a clock control circuit for detecting the SSO noise and adjusting phase of the clock signal to suppress the SSO noise.

Semiconductor device having output circuit adaptively suppressing SSO noise

There are intended to provide a semiconductor memory device capable of data access with higher speed and improvement of data transfer rate by shortening refresh operation cycle by stable low-current-consumption operation, and a control method of such a semiconductor memory device. In advance to the refresh operation mode signal M(I), control signal SW is outputted. Consequently, the switching sections select stored address bus Ladd from each storing section and stored-redundancy-judgment-result bus LJ and output address information subject to refresh operation to a word-line-driving-system circuit. After the address information from each storing section is outputted, a control signal LCH is outputted. As a result, an address switching section selects refresh address bys Add(I) subject to next refresh operation and each storing section stores address Add(I) fetched in an internal address bus IAdd and its redundancy judgment result RJ(I).

Semiconductor memory device and control method thereof

A delay circuit including a delay section having two or more predetermined delay stages is disclosed. Each predetermined delay stage adds a predetermined delay time to an input signal. The delay circuit also includes selecting switch sections. At least one of the selecting switch sections includes: a buffer section for receiving a delayed input signal from one of the delay stages and a selecting section means directly connected to the buffer section for activating the buffer section to establish a delay path, wherein an output signal from the delay path has a desired delay time.

Growing community of inventors

Kasugai, Japan

Kazufumi Komura