Fujitsu Semiconductor Limited

Kazuaki Yamane

Shoichiro Kawashima

Yasuhiro Fujii

Kazuaki Takai

Keizo Morita

Mitsuhiro Ogai

Hirokazu Yamazaki

A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.

Growing community of inventors

Yokohama, Japan

Kazuaki Yamane