Renesas Electronics Corporation

Kazuaki Terashima

Hiroshi Ikeda

Yuki Kajiwara

Rajesh Ghimire

Akihiro Yamamoto

Manabu Koike

Isao Nagayoshi

Yonghua Wang

A second memory has n banks accessible in parallel, and stores pixel data. An input DMA controller respectively transfers the pixel data stored in the second memory to n multiply-accumulate units by using n input channels. A sequence controller controls the input DMA controller so as to cause a first input channel to transfer the pixel data in a first pixel space of the input bank to a first multiply-accumulate unit and cause a second input channel to transfer the pixel data in a second pixel space of the same input bank to a second multiply-accumulate unit.

Semiconductor device

A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.

A second memory stores a plurality of input data sets DSi composed of a plurality of pieces of input data. N multiply-accumulate units are capable of performing parallel processings, and each performs a multiply-accumulate operation on any one of the plurality of weight parameter sets and any one of the plurality of input data sets. A second DMA controller transfers the input data set from the second memory to the n multiply-accumulate units. A measurement circuit measures a degree of matching/mismatching of logic levels among the plurality of pieces of input data contained in the input data set within the memory MEM, the sequence controller controls the number of parallel processings by the n multiply-accumulate units based on a measurement result by the measurement circuit.

A semiconductor device capable of reducing power consumption is provided. A group controller detects a zero weight parameter having a zero value among 'n×m' weight parameters to be transferred to a weight parameter buffer. Then, when receiving the zero weight parameter as its input, the group controller exchanges the “n×m” weight parameters to be transferred to the weight parameter buffer so that all multiplication results of the “n” multipliers included in a target multiplier group that is one of the “m” multiplier groups are zero. The group controller controls the target multiplier group to be disabled, and exchanges the “n×m” pixel data to be transferred to the data input buffer, based on the exchange of the “n×m” weight parameters.

The semiconductor device includes an image signal processor, a scaler, and an ROI (Region of Interest) controller. The image signal processor executes image processing including demosaic processing and stores the image after the image processing in memory. The scaler reduces the capture image from the image sensor to generate a reduced entire image and causes the image signal processor to execute image processing on the reduced entire image. The ROI controller cuts out a partial region of the captured image from the image sensor to generate an ROI image and causes the image signal processor to execute image processing on the ROI image.

Semiconductor device and image processing system for processing regions of interest images

A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.

Semiconductor device capable of performing software lock-step

A mobile object control system has an SfM unit detecting distance to an object imaged by a monocular camera by using the SfM algorithm, a first-stop-position output unit outputting a first stop position, a second-stop-position calculating unit calculating a second stop position closer than the first stop position, and a control unit controlling travel of a mobile object. The control unit controls the mobile object so as to stop at the second stop position. When a predetermined starting condition is satisfied, the control unit controls the mobile object so as to start. The SfM unit detects the distance to an object by using an image captured by the monocular camera after the mobile object starts. When a result of detection of the distance of the object by the SfM unit is obtained, the control unit uses the detection result for control of the travel.

Mobile object control system, mobile object control method, and program

Image processing is made efficient. An image processing apparatus according to an embodiment includes a line memory, a plurality of pipelines, and a line memory control circuit that controls data reading from the line memory to processing units. The processing unit includes a first operator that performs a first arithmetic operation, a second operator which performs a second arithmetic operation based on first intermediate data based on an arithmetic operation result of the first operator and which calculates second intermediate data according to the first intermediate data of when peripheral pixels are sequentially changed, third operators which perform a third arithmetic operation based on the first intermediate data and which calculate third intermediate data according to the first intermediate data of when the peripheral pixels are sequentially changed, and delay elements that delay the third intermediate data.

Image processing apparatus, image processing method, and vehicle control apparatus

An in-vehicle image processing device capable of appropriately monitoring areas forward of, around, and rearward of a vehicle is provided at low cost. The device is for mounting on a vehicle and includes a camera, an image processing unit, and a determination unit. With a reflector provided in front of the camera, the camera can image, for display in a frame at a time, a first area forward of the vehicle and a second area, e.g. an area around the vehicle. In the image processing unit supplied with such image data from the camera, either the first-area image or the second-area image is appropriately processed whereas image processing is omitted for the other image. Alternatively, both images are subjected to a same image processing. The determination unit supplied with vehicle speed information supplies appropriate control instruction information based on the current vehicle speed to the image processing unit.

In-vehicle image processing device and semiconductor device

To achieve an accurate transfer of control from a system to a driver, a semiconductor device includes: a recognition unit that recognizes an object present in the periphery of a vehicle based on a result of observation of the periphery of the vehicle; a route calculation unit that calculates, based on the recognized object, a travel route for the vehicle in an automatic control mode for automatically controlling the vehicle; and a mode control unit that transfers the vehicle from the automatic control mode to a manual control mode for controlling the vehicle according to an operation by a driver, when a travel route to avoid the recognized object cannot be calculated.

Semiconductor device and control method

The invention is intended to reduce overall image degradation when frame interpolation is performed by means of an adaptive image compression technique. A compression unit which adaptively compresses input image data, determines an error rate, i.e., a quantity of data loss, depending on input image data. A compression rate is set, depending on the determined error rate (or the quantity of data loss). For an image that is likely to be degraded by compression because of a large error rate determined for it, a process of generating an interpolated image by an interpolated image generating unit is disabled and an original image is used instead of an interpolated frame.

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Kawasaki, Japan

Kazuaki Terashima