Renesas Technology Corp.

Mitsubishi Electric System Lsi Design Corporation

Mitsubishi Electric System

Lsi Design Corporation

Kazuaki Tanida

Ryosuke Okuda

Katsuya Mizumoto

Hiroshi Shirota

A data/clock recovery circuit can recover high-rate data using the data as a clock signal. It includes an edge detector, a clock selection signal generating circuit, a clock selection circuit and a synchronizing circuit. The edge detector generates edge position information using a receiver output as a clock signal. The clock selection signal generating circuit generates a clock selection signal in response to the edge position information using the receiver output as the clock signal. The clock selection circuit selects a recovered clock signal from a clock signal group in response to the clock selection signal. The synchronizing circuit synchronizes the receiver output using the recovered clock signal, and outputs it as a synchronized data signal.

Data/clock recovery circuit for recovering data and clock signal with high accuracy

The number of pulses of a clock signal CLK-A is circularly counted in a count range from '0' to '7', and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of &#x201c;3&#x201d; and &#x201c;7&#x201d;, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.

Data transfer device for transferring data between blocks of different clock domains

Growing community of inventors

Hyogo, Japan

Kazuaki Tanida