Fujitsu Corporation

Nec Corporation

Kazuaki Satoh

Norikazu Ozaki

Manabu Watanabe

Kenji Iida

Kiyokazu Moriizumi

Kiyotaka Seyama

Hitoshi Kanai

Shunichi Kikuchi

Misao Umematsu

Kenichiro Yamada

Haruo Sorimachi

Naoki Mukoyama

Yasuhiro Usui

Makoto Sumiyoshi

Zhiyi Song

Kanji Nagashima

Hideki Ota

Noritoshi Sugawara

The magnetoresistance is measured for a magnetoresistive layered-structure, such as a spin valve film, prior to formation of an upper shield layer as well as patterning of a lower shield layer. The magnetic influence of the upper and lower shield layers can completely be eliminated during the measurement of the magnetoresistance. The magnetoresistive layered-structure is allowed to reliably receive the magnetic field over a wider range including a lower magnetic field range. It is accordingly possible to measure the magnetoresistance properly reflecting the magnetic characteristic of the magnetoresistive layered-structure. It is possible to find deficiency of a magnetoresistive read element at an earlier stage of the method.

Method of accurate evaluation on magnetoresistive read element

The method comprises forming a plurality of wiring pattern layers on the front surface of a substrate. In the process of forming the wiring pattern layers, an insulator protection film keeps covering over the wiring pattern on the back surface of the substrate. When the formation of the wiring pattern layers has been completed on the front surface of the substrate, a penetrating hole is bored in the cured or hardened insulator protection film. The penetrating hole may be utilized as a conductive via or a conductive through hole. A wiring pattern layer is then formed over the hardened insulator protection film on the back surface of the substrate. It is possible to omit an additional process for removing the insulator protection film. The method contributes to further facilitation of production process and further reduction in production cost.

Method of producing double-sided circuit board

A multi-layer wiring substrate includes a main substrate and a plurality of insulating films stacked on the main substrate. The plurality of insulating films have wiring patterns formed on wiring regions thereof and dummy wiring patterns formed on peripheral regions of the wiring regions. The wiring patterns include signal wiring patterns, power supply wiring patterns, and vias. The dummy wiring patterns correspond to the wiring patterns, respectively.

Multi-layer wiring substrate

In an N-bit address trap comparator, an N-bit address trap register stores an N-bit reference address, a bit-by-bit comparator compares an N-bit address with the N-bit reference address bit-by-bit, and an all-bit comparator detects whether or not all outputs of the bit-by-bit comparator have the same value. In a test mode the N-bit reference address is reset so that a first bit of the N-bit reference address is caused to be a first binary value and other bits are caused to be a second binary value. Also, the second binary value is set in all bits of the N-bit address, and then, the N-bit reference address is shifted within the N-bit address trap register.

Address trap comparator capable of carrying out high speed fault detecting test

To operate faster, a memory system includes a central processing unit (CPU) for executing a first instruction, and for outputting first, second and third signals, a memory device for storing first data and the first instruction, a first buffer for storing second data, a controller for writing the second data into the memory device when the controller receives the first signal, for reading the first data from the memory device after writing the second data into the memory device when the controller receives the second signal, and for reading the first instruction from the memory device and sending the first instruction to the CPU before writing the second data into the memory device when the controller receives the third signal.

Single-chip memory system including buffer

A method for forming bumps including the steps of forming bumps on a dummy wafer. The dummy wafer is diced into dummy chips and the bumps formed on the dummy chips are inspected. Thus only good bumps are transferred to a real chip on which circuit patterns are formed.

Method for forming bumps using dummy wafer

A multi-layer film substrate comprising at least two laminated insulating layers composed of a polyimide having a low thermal expansion, wherein an adhesion layer composed of an Si-containing or SiO.sub.2 -dispersed polyimide is interposed between the low thermal expansion polyimide layers. The substrate is produced by laminating at least two insulating layers composed of a polyimide having a low thermal expansion, wherein the low thermal expansion polyimide layers are laminated through an adhesion layer composed of an Si-containing or SiO.sub.2 -dispersed polyimide.

Multi-layer film substrate and process for production thereof

A thin film multi-layer structure includes a plurality of metal thin film layers, and a plurality of layers made of polyimide. The plurality of metal thin film layers and the plurality of layers made of polyimide are stacked in a predetermined order, the plurality of layers made of polyimide being grouped into a first group and a second group including at least a layer located at a top of the plurality of layers. A Young's modulus value of the polyimide of which each layer in the second group is made is less than that of the polyimide of which each layer in the first group is made and a thermal expansion coefficient of the polyimide of which each layer in the first group is made is less than that of the polyimide of which each layer in the second group is made.

Thin film multi-layer structure and method for manufacturing the same

A multilayer structure is fabricated by forming a conductive layer on an insulative substrate. A first conductive pattern is formed on the first conductive layer and a resist layer having a via hole therethrough is formed on the first pattern. A via lead is formed in the via hole by electrically plating a metal therein utilizing the first layer as a lead for the plating process. The resist and the exposed part of the first layer are removed and a polyimide layer having a thermal expansion coefficient that is equal to that of the via lead is formed over the substrate. The surface of the polyimide layer is etched until the via lead top segment protrudes to a predetermined height above the surface of the etched polyimide layer. A second pattern is formed on the polyimide layer and the exposed lead segment by a plating process.

Multilayer circuit structure having projecting via lead

A multi-chip module (MCM) having semiconductor chips on a top surface of multi-layered interconnection circuits formed on a planar surface of a substrate including: (a) multi-layered interconnection circuits comprising alternatively laminated interconnection layers with insulating layers, and thermal contacts, each of the thermal contacts comprising successively laminated interconnection layers on a bottom and on side-walls of a vertical hole penetrating a plurality of the insulating layers, and a thermal conductor filling the vertical hole on the successively laminated interconnection layers, and (b) a plurality of the semiconductor chips attached to the thermal conductor. In a preferred embodiment, a V-shaped vertical hole is formed in the insulating layers of polyimide for a thermal contact, copper films are successively laminated thereon, unpatterned copper and gold films are deposited thereon, and the entire surface of the metal film including the hole is coated by a silver-powder containing epoxy film, to which semiconductor chips are adhered.

Multi-chip module having thermal contacts

A method of producing a thin film multi-layered substrate involving the steps of subjecting a copper wiring formed on a substrate to chromate treatment with an aqueous solution containing potassium bichromate or sodium bichromate as a principal component and containing chromic anhydride blended therewith, forming an interlevel insulating film consisting of photosensitive polyimide on the copper wiring, and exposing and developing the photosensitive polyimide film to form a pattern. A miniature pattern can be formed at a high speed and with high production yield.

Method of producing thin film multi-layered substrate

A conductive pattern layer structure includes an insulating member containing polyimide, a patterned thin film formed on the insulating member, and a patterned conductive layer formed on the thin film. The patterned conductive layer contains copper. Further, the layer structure includes a patterned barrier layer covering an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.

Patterned chromium barrier layer with flange-like structure

A method of forming a conductive pattern layer structure includes providing an insulating member containing polyimide, forming a patterned thin film on the insulating member, and forming a patterned conductive layer on the thin film. The patterned conductive layer contains copper. Further, a barrier layer can be patterned to cover an upper surface and side surfaces of the patterned conductive layer to prevent copper from being diffused into another insulating layer formed around the patterned barrier layer.

Method of producing conductive pattern layer structure

A multilayer structure of the invention is fabricated by patterning a first electrically conductive layer on an insulative substrate; coating a polyamic acid resin layer all over the first electrically conductive layer; piercing a metal pin into the resin layer so that a first end of the pin contacts and is cold-welded to the first electrically conductive layer; hardening said polyamic acid resin to become polyimide resin; and patterning a second electrically conductive layer over the resin layer and the second end of the pin exposed from the surface of the resin layer. The cold-welding of the pin to the first conductive layer allows a reliable connection thereof. Moreover, this structure and method allow an improved flatness of each layer, resulting in an achievement of a larger number of the multilayers without the prior art problem of pattern breakage caused from less flat layers. The polyimide resin, which is not required to be photosensitive in the above fabrication method, can be employed so that its thermal expansion coefficient is same as the pin. Accordingly, no thermal stress is generated at the connection between the pin and the second conductive layer, resulting in an improved reliability of the connection.

Multilayer structure and its fabrication method

A multilayer structure is fabricated by forming a conductive layer on an insulative substrate. A first conductive pattern is formed on the first conductive layer and a resist layer having a via hole therethrough is formed on the first pattern. A via lead is formed in the via hole by electrically plating a metal therein utilizing the first layer as a lead for the plating process. The resist and the exposed part of the first layer ar removed and a polyimide layer having a thermal expansion coefficient that is equal to that of the via lead is formed over the substrate. The surface of the polyimide layer is etched until the via lead top segment protrudes to a predetermined height above the surface of the etched polyimide layer. A second pattern is formed on the polyimide layer and the exposed lead segment by a plating process.

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Kawasaki, Japan

Kazuaki Satoh