Sharp Kabushiki Kaisha Corporation

Kazuaki Ochiai

Makoto Ihara

Yoshiji Ota

A semiconductor memory device has a plurality of pairs of bit lines and one or more pairs of redundant bit lines to replace faulty bit lines, if any. The redundant bit lines are connected with a first pair of data lines, which is connected to a differential amplifier, by respective second switches, and the bit lines are connected with a second pair of data lines by respective first switches. A third switch is provided between the first and second data lines, and the second data lines are connected to or disconnected from the first data lines by the third switch. There are also provided column decoders connected to the respective first switches and redundant column decoders connected to both the respective second switches and the third switch. When either redundant column decoder outputs a redundant signal for connecting the redundant bit lines to the first data lines, the third switch is turned off to disconnect the second data lines from the first data lines and therefore from the differential amplifier. On the other hand, when every redundant column decoder outputs a non-redundant signal for disconnecting the redundant bit lines from the first data lines, the third switch is turned on to connect the second data lines to the first data lines and therefore to the differential amplifier.

Semiconductor memory device capable of replacing faulty bit lines with

A semiconductor memory device has a multibit parallel test function and a method of testing such a memory device. The memory device comprises a multibit parallel writing circuit (2) and a multibit parallel check circuit (3). The method comprises the steps of: inputting test data into a memory unit through an input (4) while setting the multibit parallel writing circuit (2) to the ON state by a control circuit; reading out the multibit test data from the memory unit, while setting the multibit parallel check circuit (3) to the OFF state, thereby conducting the test of the multibit parallel writing circuit (2) inputting multibit test data into the memory unit through the input, while setting the multibit parallel writing circuit (2) to the OFF state by the control circuit; and reading out the multibit test data from the memory unit, while setting the multibit parallel check circuit (3) to the ON state, thereby conducting the test of said multibit parallel check circuit (3).

Semiconductor memory device having a multibit parallel test function and

A semiconductor memory device has an array of examined memory cells, and reference memory cells in a column. The examined memory cells in each column and the reference memory cells are connected with respective pairs of complementary bit lines connected with sense amplifiers. Each reference memory cell and the examined memory cells in each row are connected with corresponding word lines. The device also has a line data memory circuit, a bit line select circuit and a plurality of output evaluation circuits connected with the bit line pairs for the examined memory cells. In a test mode, identical data is simultaneously written to the reference and examined memory cells connected with each word line. The line data memory circuit outputs data from the reference memory cell as expected data, in response to which, the bit line select circuit selects one of the bit lines for each of the examined memory cells when the expected data is LOW, and the other of the bit lines when the expected data is HIGH. Each output evaluation circuit simultaneously detects an output from a corresponding examined memory cell via the one bit line or the other bit line selected in accordance with the expected data, and outputs a signal indicating coincidence or non-coincidence between the output signal detected and the expected value. Thus the device tests its own operation through a parallel access to the memory cells.

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Tenri, Japan

Kazuaki Ochiai