Seiko Instruments Inc

Kazuaki Kubo

Masanori Miyagi

Yoshikazu Kojima

Yutaka Saitoh

Haruo Konishi

Tetsuya Kaneko

Toru Machida

Toru Shimizu

Yukio Suzuki

Youichi Endo

A memory circuit allowing data to be read when a source voltage decreases below the threshold of a selecting transistor comprises a selecting transistor and a series-connected memory transistor, a power source for supplying a source voltage, a voltage detecting circuit for detecting a voltage of the source voltage, a boosting circuit for boosting the source voltage when it has fallen to a value near or below the threshold voltage of the selecting transistor, and a boosted voltage detecting circuit for detecting the boosted voltage and controlling the boosting circuit to boost the source voltage to a value within a range having a lower limit greater than the threshold voltage of the selecting transistor. The boosting circuit generates a boosted voltage that is applied to a word line via high-voltage switch.

Memory circuit

A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.

Semiconductor device and manufacturing method thereof

In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region,having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region,having a second impurity concentration determined by doping an impurity to the region selected by a pattern,of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region,having the first impurity concentration and the channel region,having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.

An EEPROM operable at a reduced power source voltage comprises a decoder circuit for decoding input signals, a memory array for storing the decoded, a reading circuit for operating the decoder circuit and the memory array, and for reading out data stored in the memory array, and a writing circuit for operating the decoder circuit and the memory array, and for writing data to the memory array. The EEPROM is divided into a first circuit area comprising a plurality of first transistors driven by a first power source voltage, an absolute value of a threshold voltage of the first transistors in the first circuit area being within the range of approximately 0.3 V to 0.7 V, the first circuit area including at least the reading circuit, and a second circuit area comprising a plurality of second transistors driven by a second power source voltage, an absolute value of a threshold voltage of the second transistors in the second circuit area being within the range of approximately 0.7 V to 0.9 V, the second circuit area including at least the writing circuit.

Integrated logic circuit and EEPROM

An EEPROM capable of arbitrarily setting a write time includes a timer circuit connected to a trimming circuit for determining a write time, and a trimming redundant memory array used for storing trimming data to be supplied to the trimming circuit in accordance with a predetermined write time so that the write time can be arbitrarily set. A series of calibration operations are performed such that the trimming data is read from the trimming redundant memory and supplied to the trimming circuit and the timer circuit is controlled so as to set the write time to a desired value. The latter operation is carried out in parallel to a normal write operation. Accordingly, neither special instructions nor an additional time period are required to perform the calibration operation, and a stable operation can be achieved in less time.

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Chiba, Japan

Kazuaki Kubo