Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Kazuaki Isobe

Noboru Shibata

Seiichi Mori

Toshiharu Watanabe

Masataka Takebuchi

Akira Umezawa

Yoshiharu Hirata

Takamichi Kasai

Kanji Osari

According to one embodiment, a semiconductor memory device includes first to nth string units (n being a natural number of 3 or more), a plurality of layers of word lines, and (n&#x2212;1) layers of select gate layers. The first to nth string units each includes a memory string. The memory string includes a plurality of memory cells and a plurality of select transistors connected in series in a first direction. The (n&#x2212;1) layers of select gate layers include first to (2&#xd7;(n&#x2212;1))th select gates electrically isolated from each other. The first string unit is selected by the first to (n&#x2212;1)th select gates. The kth string unit (k being not less than 1 and not more than n) is selected by the kth to (n+k&#x2212;2)th select gates. The nth string unit is selected by the nth to (2&#xd7;(n&#x2212;1))th select gates.

Semiconductor memory device

According to one embodiment, a nonvolatile semiconductor storage device includes a first well region of a first conductivity type, a second well region of the first conductivity type, a third well region of a second conductivity type, a bit line and a column decoder. A first cell array including a plurality of memory cells is formed in the first well region. A second cell array including a plurality of memory cells is formed in the second well region. The third well region includes the first and second well regions. The bit line is connected to the memory cells included in the first cell array and the memory cells included in the second cell array. The column decoder is connected to the bit line.

Nonvolatile semiconductor storage device with multiple well regions and a shared bit line

A plurality of memory cells each constituted of a memory cell transistor having a gate electrode in a laminated structure composed of a charge storage layer and a control gate layer and a select transistor having source/drain diffusion layers while one of the source/drain diffusion layers is shared by the memory cell transistor are arranged in and on a semiconductor substrate. The impurity concentration of the source/drain diffusion layer shared by the memory cell transistor and the select transistor in each of the plurality of memory cells is set lower than the impurity concentration of the other source/drain diffusion layers in each of the memory cells.

Semiconductor memory device and method of manufacturing the same

A semiconductor device in which a channel region of MOS transistor is provided not to include a non-flat active region end portion and a manufacturing method thereof is disclosed. According to one aspect, there is provided a semiconductor device comprising a semiconductor substrate, a device isolation separating active region, wherein at least a portion of the device isolation is provided in the semiconductor substrate, and a memory cell including a memory cell transistor that comprises a channel region separated by a slit and constituted of a flat active region alone, a charge storage layer provided on a gate dielectric on the channel region, and a first gate electrode provided on an inter-electrode dielectric so as to cover the charge storage layer, and a select transistor that comprises a second gate electrode provided on the gate dielectric on the active region and electrically connected to a wiring.

Semiconductor device and manufacturing method of same

A semiconductor device including a memory cell having a memory transistor and select gate transistor and a peripheral transistor is disclosed. The memory transistor has a stacked gate structure formed by sequentially stacking a gate insulating film, first gate electrode, inter-poly insulating film, and second gate electrode on a semiconductor substrate. The select gate transistor has a stacked gate structure identical to the memory transistor, and selects the memory transistor. The peripheral transistor forms a peripheral circuit of the memory cell, and has a gate electrode having a single-layer structure. A through hole reaching the first gate electrode is formed in the second gate electrode and inter-poly insulating film positioned on an element isolation film of the select gate transistor. A contact plug buried in this through hole electrically connects the second gate electrode and first gate electrode.

Flash EEPROM cell and method of fabricating the same

A first side-wall film is formed on the sides of a gate electrode of a high-voltage transistor, and a second side-wall film is provided on the first side-wall film. The first side-wall film has an etching rate lower that of a pre-metal dielectric, and the second side-wall film has an etching rate substantially equal to that of the of the pre-metal dielectric. The LDD of the high-voltage transistor is provided in that part of the semiconductor substrate which lies right below the first and second side-wall films. The source/drain diffusion layer of the high-voltage transistor is formed in that part of the substrate which is outside the second side-wall film. A first side-wall film having an etching rate lower than that of the pre-metal dielectric and/or a second side-wall film having an etching rate substantially equal to that of the pre-metal dielectric are provided on the sides of the gate electrode of the low voltage transistor. The LDD of the low voltage transistor is provided in that part of the substrate which lies right below the first side-wall film. The drain/source diffusion layer of the low voltage transistor is provided in two continuous parts of the substrate which lie, respectively, right below and outside the second side-wall film.

Semiconductor device having MISFETs

A cell array region and a peripheral transistor region are provided. In the cell array region, a plurality of memory cell transistors are formed, and element regions of the memory cell transistors are isolated by an embedded isolation region. In the peripheral transistor region, a plurality of peripheral circuit transistors are formed, and element regions of the peripheral circuit transistors are isolated by an embedded isolation region. Isolation end portions of the gate electrode of each peripheral circuit transistor do not fall in grooves of the embedded isolation region but is positioned to be horizontal to the center part of the gate electrode.

Growing community of inventors

Yokohama, Japan

Kazuaki Isobe