Infineon Technologies Ag

Qimonda Ag

Kazimierz Szczypinski

Helmut Fischer

Johann Pfeiffer

Martin Brox

Alessandro Minzoni

Patrick Heyne

Georg Georgakos

Alexander Benedix

Andre Schaefer

Eckhard Brass

Margaret Freebern

Athanasia Chrysostomides

Andre Schäfer

Jens Polney

Rajashekhar Rao

Wen-Ming Lee

An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided.

Integrated circuit and method for manufacturing the same

Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a write control circuit for executing write commands, wherein the write control circuit is designed to start executing a write command when a write signal is applied to the write signal connection during an edge of the system clock signal.

Control circuit in a memory chip

Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.

Integrated circuit and programmable delay

Methods, systems, and articles of manufacture for transferring control commands to a memory device. In one embodiment, the memory device comprises at least one serial command terminal with a downstream serial command decoder for receiving and decoding external command code as a serial bit sequence. Embodiments of the invention also disclose a memory controller comprising both a multiplicity of parallel command outputs and at least one serial command output for transmitting command code to the memory device as a serial bit sequence.

Digital RAM memory circuit with an expanded command structure

A memory includes a row address latch. The row address latch includes a first stage configured to latch a row address for a memory read or write operation, and a second stage configured to latch a row address for a memory bank auto-refresh. The row address latch provides the row address from the first stage in response to an activate command and provides the row address from the second stage in response to a directed auto-refresh command.

Directed auto-refresh for a dynamic random access memory

The invention involves a clock pulse synchronization process as well as a device to be used in the synchronization of clock pulses, including a first delay apparatus with variably controllable delay period, in which a clock pulse or a signal derived from it, has a variably controllable delay period imposed on it and is then emitted as a delayed signal. In addition to the first delay apparatus with variably controllable delay period, a second delay apparatus with variably controllable delay period is provided.

Device to be used in the synchronization of clock pulses, as well as a clock pulse synchronization process

A semiconductor memory includes a control circuit for generating an internal read command signal depending on an externally applied read command signal. A clock generating circuit generates a system clock signal and a time shifted clock signal generated by a DLL circuit. A latency counter circuit comprises a first control circuit for generating a first control signal and a second control circuit for generating a second control signal. The first control signal is used to latch the internal read command signal in one of FIFO-latching cells. The latching is carried out in a system clock domain. The second control signal is used to release a time shifted internal read command signal from one of the FIFO-latching cells in a DLL clock domain. The relationship between first and second control signals determines a CAS latency by which data items appear at a data terminal synchronous with an externally applied clock signal.

Integrated semiconductor memory device for synchronizing a signal with a clock signal

An integrated circuit, in particular an integrated memory circuit, has an input circuit for the purpose of receiving a signal. The input circuit has an activation input for an activation signal in order to activate the input circuit, in a manner dependent on the activation signal, for the purpose of receiving signals.

Integrated circuit having an input circuit

Integrated module having a circuit and a plurality of input/output terminals, each of the input/output terminals being connected to a driver circuit for driving output signals and to a reception circuit for receiving input signals, a first delay element with a first delay time being provided in the integrated module, which delay element can be connected into a signal path of a circuit-internal signal or can be disconnected, in order to delay or to accelerate the circuit-internal signal, wherein provision is made of a first test delay element at a first input/output terminal pair which is embodied in a manner structurally identical to the first delay element, in order, in a test operation, to determine the delay time by means of the signal propagation time between the two input/output terminals of the first input/output terminal pair.

Integrated module having a delay element

In a semiconductor memory, there is capacitive coupling between bit lines that largely run in parallel. Outer sections of the bit lines are connected via respective switches to a sense amplifier arranged between the switches. When a memory cell is being read, the capacitive interference by other bit lines that are not coupled to the memory cell being read is kept as low as possible before the start of amplification by the sense amplifier by turning on the switches in that bit line. During the amplification phase, the remote outer section of that bit line is disconnected using the appropriate switch. In one embodiment, the capacitance of the bit line that is not connected to the memory cell to be read is increased further by additionally activating a precharging circuit.

Method for reading a memory cell in a semiconductor memory, and semiconductor memory

The invention involves a component with a connection (), as well as at least one further connection (), whereby differential input clock pulses (CLK, CLK; /CLK, /CLK) can be applied to the connections (), or a single input clock pulse (CLK, CLK) applied to the connection () and/or to the further connection ()&#x2014;, and where the component in addition has a first and a second pulse relay device (), where the first pulse relay device () has been provided for relaying differential input clock pulses (CLK, CLK; /CLK, /CLK), and the second pulse relay device () for relaying a single input clock pulse (CLK, CLK).

Semi-conductor component with clock relaying device

So that semiconductor memory devices can be used optimally with regard to different possible operating frequencies, according to the invention, a register area is formed in which frequency information with regard to a present operating frequency can be stored in coded form and be retrieved for a configuration and adaptation of the semiconductor memory device.

Semiconductor memory device

The invention relates to a nonvolatile NOR two-transistor semiconductor memory cell, an associated semiconductor memory device and a method for the fabrication thereof, in which one-transistor memory cells are located in an active region formed in annular fashion and are driven via associated word lines. In this case, the source regions of the one-transistor memory cells are connected via a source line, while the drain regions are connected via corresponding drain lines. A reduced space requirement for the two-transistor semiconductor memory cell is obtained in particular on account of the annular structure of the active regions.

Nonvolatile NOR two-transistor semiconductor memory cell and associated NOR semiconductor memory device and method for the fabrication thereof

An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged regularly in cell arrays, and signal interconnect structures with amplification transistors for bit line signal amplification. The amplification transistors are of identical design and they lie opposite one another in pairs in adjacent transistor rows. Signal interconnects, which are associated with the transistor rows and run parallel thereto, supply actuation signals. The signal interconnects for the actuation signals have the same arrangement symmetry as the amplification transistors, which means that the amplification transistors in adjacent transistor rows are in the same signal interconnect proximity.

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Munich, Germany

Kazimierz Szczypinski