Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Device Engineering Co., Ltd.

Kayoko Saito

Masanori Odaka

Mitsugu Kusunoki

Nobuo Tamba

Toshiro Hiramoto

Masayuki Ohayashi

Goro Kitsukawa

Hiroaki Nambu

Kazuo Kanetani

Hisayuki Higuchi

Noriyuki Homma

Kunihiko Yamaguchi

Youji Idei

Hiroyasu Ishizuka

Yoshiaki Sakurai

Kenichi Ohata

Shinichiro Masuda

A first clamp circuit and a second clamp circuit stacked thereon in vertical respectively for clamping unwanted level voltages are provided between the high potential side power source and low potential side power source and an intermediate node formed by vertical stacking of the first clamp circuit and second clamp circuit is coupled with the power source for internal circuit. Since a capacitor originally provided in the internal circuit is allocated in parallel to the first clamp circuit, impedance is reduced due to existence of the capacitor and potential difference due to over-current flowing in the chip is reduced. Accordingly, potential difference due to over-current flowing into the chip may be reduced and static electricity dielectric strength can be improved by allowing higher over-current. Thereby, impedance when the clamp circuits are stacked in two stages.

Semiconductor integrated circuit device

The present invention provides a semiconductor integrated circuit device equipped with an input circuit capable of stably performing a high-speed operation up to a low voltage. A rail to rail circuit constitutes a differential input circuit, and a circuit similar to such a differential input circuit is used to constitute a bias circuit. A pair of output terminals of a differential circuit constituting such a bias circuit is commonly connected to form a bias voltage corresponding to a middle point. The bias voltage is supplied to the gates of current source MOSFET and the gates of cascode-connected MOSFETs in the differential input circuit, and the gates of the corresponding current source MOSFETs and cascode-connected MOSFETs in the bias circuit corresponding to itself.

A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced. Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion. Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.

Semiconductor integrated circuit device including input circuitry to

A semiconductor integrated circuit device including a level conversion circuit in which the simplifying of the circuit and the increasing of the speed of operation have been attained is provided. A pair of complementary output signals amplified to a required signal level by a current switch circuit including differential transistors which receive an input signal and a reference voltage are inputted into a pair of emitter follower circuits. An emitter follower output transistor is driven by an output signal from one emitter follower circuit, while an N-channel MOSFET provided between the output transistor and a current source used as a load is driven by an output signal from the other emitter follower circuit, to obtain a level-amplified output signal from an emitter of the output transistor. The speed of an operation of the circuit device can be increased to a high level owing to a simple circuit in which a level, which is required to attain an output amplitude, of complementary output signals is secured by the current switch circuit, the amplified complementary signals being inputted into the emitter follower circuit to directly drive the output transistor.

Semiconductor integrated circuit device and memory consisting of

Growing community of inventors

Hamura, Japan

Kayoko Saito