Advanced Micro Devices Corporation

Intel Deutschland Gmbh

Globalfoundries Inc.

Intel Mobile Communications Gmbh

Intel Mobile Communications Technology Dresden Gmbh

Shenzhen Goodix Technology Co., Ltd.

Commsolid Gmbh

Kay Hesse

Suresh B Periyacheri

Wei-Yu Chen

Lars Melzer

Sven Mueller

Kevin Badgett

Markus Seuring

Markus Krause

Kai Eichhorn

A circuit for software tracing in a system on chip is described as including a plurality of components, each component having at least one local processor connected to a first communication bus; and each component being connected to a second communication bus. The circuit may further include a separate trace data bus being configured to transmit trace data generated by code running on the components. A method associated with software tracing on such a circuit is also disclosed.

Circuit and method for software tracing

Implementations relate to a hybrid finite state machine that is based on a micro-coded processor and the use of look-up tables to implement combinational logic. Micro-coding is used to describe the state transitions of the FSM and look-up tables are used to determine the conditions for state transitions and to generate the outputs as a function of the state.

Finite state machine for system management

In a complex semiconductor device including embedded memories, the round trip latency may be determined during a memory self-test by applying a ping signal having the same latency as control and failure signals used during the self-test. The ping signal may be used for controlling an operation counter in order to obtain a reliable correspondence between the counter value and a memory operation causing a specified memory failure.

Latency detection in a memory built-in self-test by using a ping signal

A clock domain separation device and a method for operating the device is provided for separating two clock domains of a bus system in a system-on-chip (SoC). The clock domain separation device is a hardware module that acts as a guarding between the two clock domains that contain either bus end, and is generally applicable with handshake-type bus protocols. The clock domain separation module allows for each clock domain to switch its clock on and off independently from the state of the other clock domains, without risking data loss or protocol violation.

Circuitry system and method for connecting synchronous clock domains of the circuitry system

A circuit arrangement includes a plurality of functional units each of which comprises a plurality of data processing modules and a local controller. The plurality of data processing modules run a common system clock and are connected by a streaming data bus running a handshake-type streaming data transfer protocol. A profiling module of the circuit arrangement assesses control signals tapped at predefined interfaces of the streaming data bus during real time operation, for determining link performance and communication patterns for profiling and debugging purposes, and hence constitutes a simple and low cost approach for assessing intra-component and inter-component link performance and communication patterns on large SoCs. A method for profiling data flow for use in such a circuit arrangement is also provided.

Method and arrangement for streaming data profiling

Integrated circuits with memory built-in self test (MBIST) circuitry and methods are disclosed that employ enhanced features. In one aspect of the invention, an integrated circuit is provided having MIBST circuitry configured to serially test multiple arrays of memory elements within a component of the integrated circuit and to also conduct parallel initialization of the serially tested arrays. In another aspect of the invention, the MBST circuitry is used set the memory elements of the arrays to a first state and then to an inverse state during a burn-in operation to maintain each of the two opposing states for a desired time in order to either force a failure of the integrated circuit component or produce a pre-stressed component beyond an infancy stage.

Integrated circuit with memory built-in self test (MBIST) circuitry having enhanced features and methods

In a sophisticated semiconductor device including a large memory portion, a built-in self-test circuitry comprises a failure capturing logic that allows the capturing of a bitmap at a given instant in time without being limited to specific operating conditions in view of interfacing with external test equipment. Thus, although pipeline processing may be required due to the high speed operation during the self-test, reliable capturing of the bitmap may be achieved while maintaining high fault coverage of the test algorithm under consideration.

At-speed bitmapping in a memory built-in self-test by locking an N-TH failure

A USB (Universal Serial Bus) controller technique for implementing OTG (On-The-Go) functionality is provided. The device may have an EHCI (Enhanced Host Controller Interface) compliant host control unit, and an OTG control unit to implement an OTG state machine partly in hardware and partly in software. The OTG control unit may have an OTG control register and an OTG status register which are accessible by software. Further, the USB controller device may have a device control unit to implement device functionality and a port multiplexer to assign a physical port to either the host or the device control unit. The OTG control unit may be comprised in the port multiplexer. Further, a software driver may read the OTG status register in response to receiving an interrupt from the USB controller device, and write to the OTG control register to force the USB controller device to change its OTG state.

USB on-the-go controller

A USB (Universal Serial Bus) OTG (On-The-Go) controller device and more generally a serial bus control circuit chip are provided which have improved port handler implementations. In one example, different port handler units may be provided which selectively support host and device functionality at the respective ports. In another example, a first port handler for providing host functionality and a second port handler for providing device functionality are provided which are of substantially the same hardware structure. In a further example, at least one port handler is provided that has a low level protocol module for handling packet assembly and/or disassembly, a transfer buffer module for buffering incoming or outgoing data to average out system memory latencies, and a memory access module for generating memory requests in compliance with host and/or device functionality.

Growing community of inventors

Dresden, Germany

Kay Hesse