Lsi Corporation

Lsi Logic Corporation

Kavitha Chaturvedula

Juergen K Lahner

Balamurugan Balasubramanian

Randall P Fry

Kiran Atmakuri

Srinivas Adusumalli

Gregory Pierce

Krishna Devineni

Kiran Atkmakuri

Disclosed is a method of replicating control signal sources, comprising: receiving a description of a functional block that comprises at least one of, a plurality of multiplexer structures, a plurality of memory blocks, and a combination of at least one multiplexer structure and at least one memory block; identifying a control signal that controls said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block; and, determining a first replica control signal and a second replica control signal, said first replica control signal and said second replica control signal collectively functioning as said control signal to control said at least one of, said plurality of multiplexer structures, said plurality of memory blocks, and said combination of at least one multiplexer structure and at least one memory block.

Control signal source replication

A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a plurality of design closure categories respectively, the chip yield improvements capturing historically trends based on a plurality of previous projects, (B) calculating a plurality of targets of a current design closure project based on the statistical data, one of the targets in each one of the design closure categories respectively and (C) generating a resource report to a user that indicates a plurality of resources expected to be used the current design closure project.

Statistical design closure

A method of optimizing test code generation is disclosed. The method generally includes the steps of (A) reading from a database (i) a plurality of assertions, (ii) a testbench and (iii) a target code coverage all of a design under test, (B) generating together (i) a plurality of first test vectors to test the assertions and (ii) a plurality of second test vectors applicable to the testbench, (C) identifying one or more redundant test vector sets between the first test vectors and the second test vectors and (D) generating the test code to test the design under test on the testbench using a subset of the first test vectors and the second test vectors, the subset comprising single instances of the redundant test vector sets.

Optimizing test code generation for verification environment

A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and receiving as input criteria defining a critical multiplex structure. The first register transfer level code is analyzed to identify multiplex structures in the first register transfer level code. Each of the multiplex structures identified in the first register transfer level code is compared to the criteria defining a critical multiplex structure. Each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure is entered in a list of critical multiplex structures. The list of critical multiplex structures is generated as output.

Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code

A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.

Method of optimizing RTL code for multiplex structures

A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.

Growing community of inventors

San Jose, CA, United States of America

Kavitha Chaturvedula