Micron Technology Incorporated

Nan Ya Technology Corporation

Dow Global Technolgoies LLC

Rohm & Haas Electronic Materials LLC

Kaveri Jain

Anton J deVillers

Adam L Olson

William R Brown

Lijing Gou

Dan B Millward

Ho Seop Eom

Scott L Light

Jianming Zhou

Zishu Zhang

Yuan He

Michael D Hyatt

Xue Chen

Nicholas Hendricks

Scott Schuldenfrei

Robert Dembi

Lance Williamson

Xue (Gloria) Chen

Peter Trefonas, Iii

Phillip Dene Hustad

Jong Keun Park

Nik Mirin

Christopher Nam Lee

Anton J De Villiers

A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.

Methods of forming nanostructures including metal oxides using block copolymer materials

Self-assembled nanostructures including metal oxides and semiconductor structures comprised thereof

Methods of forming staircase structures. The method comprises forming a patterned hardmask over tiers. An exposed portion of an uppermost tier is removed to form an uppermost stair. A first liner material is formed over the patterned hardmask and the uppermost tier, and a portion of the first liner material is removed to form a first liner and expose an underlying tier. An exposed portion of the underlying tier is removed to form an underlying stair in the underlying tier. A second liner material is formed over the patterned hardmask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying tier. An exposed portion of the another underlying tier is removed to form another underlying stair. The patterned hardmask is removed. Staircase structures and semiconductor device structure are also disclosed.

Apparatus comprising staircase structures

Methods of forming staircase structures

A method of forming a semiconductor structure comprises forming pools of acidic or basic material in a substrate structure. A resist is formed over the pools of acidic or basic material and the substrate structure. The acidic or basic material is diffused from the pools into portions of the resist proximal to the pools more than into portions of the resist distal to the pools. Then, the resist is exposed to a developer to remove a greater amount of the resist portions proximal to the pools compared to the resist portions distal to the pools to form openings in the resist. The openings have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure. The method may further comprise forming features in the openings of the resist. The features have wider portions proximal to the substrate structure and narrower portions distal to the substrate structure.

Semiconductor device structures

Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first pattern. The first pattern has a first level of uniformity across a distribution of the features. A brush layer is formed across the first mask and within the features to narrow the features and create a second mask from the first mask. The second mask has a second level of uniformity across the narrowed features which is greater than the first level of uniformity. A pattern is transferred from the second mask into the material.

Methods of forming patterns with a mask formed utilizing a brush layer

Methods of forming openings in semiconductor structures

Methods of forming resist features, resist patterns, and arrays of aligned, elongate resist features are disclosed. The methods include addition of a compound, e.g., an acid or a base, to at least a lower surface of a resist to alter acidity of at least a segment of one of an exposed, acidic resist region and an unexposed, basic resist region. The alteration, e.g., increase or decrease, in the acidity shifts an acid-base equilibrium to either encourage or discourage development of the segment. Such 'chemical proximity correction' techniques may be used to enhance the acidity of an exposed, acidic resist segment, to enhance the basicity of an unexposed, basic resist segment, or to effectively convert an exposed, acidic resist segment to an unexposed, basic resist segment or vice versa. Thus, unwanted line breaks, line merges, or misalignments may be avoided.

Methods for forming resist features and arrays of aligned, elongate resist features

Photolithographic apparatus and methods are disclosed. One such apparatus includes an optical path configured to provide a first diffraction pattern in a portion of an optical system and to provide a second diffraction pattern to the portion of the optical system after providing the first diffraction pattern. Meanwhile, one such method includes providing a first diffraction pattern onto a portion of an optical system, wherein a semiconductor article is imaged using the first diffraction pattern. A second diffraction pattern is also provided onto the portion of the optical system, but the second diffraction pattern is not used to image the semiconductor article.

Lens heating compensation in photolithography

A method of forming a reversed pattern in a substrate. A resist on a substrate is exposed and developed to form a pattern therein, the patterned resist having a first polarity. The polarity of the patterned resist is reversed to a second polarity, and a reversal film is formed over the patterned resist having the second polarity. The patterned resist having the second polarity is removed, forming a pattern in the reversal film. The pattern in the reversal film is then transferred to the substrate. Additional methods of forming a reversed pattern in a substrate are disclosed, as is a semiconductor structure formed during the methods.

Methods of forming a reversed pattern in a substrate, and related semiconductor device structures

Methods of forming patterns by using a brush layer and masks

Growing community of inventors

Boise, ID, United States of America

Kaveri Jain