Cypress Semiconductor Corporation

Longitude Flash Memory Solutions Ltd.

Kaveh Shakeri

Venkatraman Prabhakar

Igor G Kouznetsov

Ryan Tasuo Hirose

Bogdan I Georgescu

Sarath Chandran Puthenthermadam

Long Hinh

Jay Ashokkumar

Helmut Puchner

Kavin Jaejune Jang

Ryan Hirose

A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than Vis coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.

Method to reduce program disturbs in non-volatile memory cells

A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Apparatuses and methods of pulse shaping a pulse signal for programming and erasing a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory cell are described. In one method a pulse shape of a pulse signal is controlled to include four or more phases for programming or erasing a SONOS memory cell. A write cycle is performed to program or erase the SONOS memory with the pulse signal with the four or more phases.

Endurance of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells

A memory cell can include at least a first programmable section coupled between a supply node and a first data node; a volatile storage circuit coupled to the first data node; and the programmable section includes a programmable transistor having a first source/drain (S/D) region shared with a first transistor, and a second S/D region shared with a second transistor; wherein the first S/D region has a different dopant diffusion profile than the second S/D region, and the programmable transistor has a charge storage structure formed between its control gate and its channel. Methods of forming such a memory cell are also disclosed.

Nonvolatile memory cells and methods of making such cells

A RECALL process in a memory circuit includes RECALLing the state of a volatile memory cell from a nonvolatile memory cell, and inverting an output of the volatile memory cell after every other RECALL.

nvSRAM with inverted recall

A process of operating a memory circuit involves RECALLing a state of a volatile memory cell from a nonvolatile memory cell, and inverting an output of the volatile memory cell after every other RECALL.

Non-volatile (NV) semiconductor memories and methods of operating the same to reduce or eliminate a need for an external capacitance are provided. In one embodiment, the memory includes a memory cell comprising a random access memory (RAM) portion and a NV memory portion, and the method comprises steps of: (i) initially erasing the NV memory portion; and (ii) on detecting a drop in power supplied to the memory, programming the NV memory portion with data from the RAM portion while powering the memory from a capacitor. On restoration of power data is recalled from the NV memory portion into the RAM portion, and the NV memory portion erased. Preferably, the capacitor is integrally formed on a single substrate with the NV memory portion and RAM portion. More preferably, the capacitor comprises intrinsic capacitance between elements of the memory formed on the substrate. Other embodiments are also disclosed.

Growing community of inventors

Campbell, CA, United States of America

Kaveh Shakeri