Jasper Display Corporation

Google Inc.

Magma Design Automation, Inc.

Kaushik Sheth

Bo Li

Edwin Lyle Hudson

David Charles McDonald

James Michael Stover

Jeffrey Tang Fung Li

Egino Sarto

Shenghua Liu

Guoqiang Chen

A memory cell for a display is disclosed. The memory cell has a current limiter on the power supply to reduce the power consumed by the memory cell during a write operation when the binary state of the memory cell is flipped. In a dense memory environment, in a display with a million or more memory cells, the incremental power reduction of each memory cell corresponds to a substantial reduction in the overall power consumed by the display.

Memory cell for a pixel of a display

A backplane suitable to pulse width modulate an array of emissive pixels with a current that is substantially constant over a wide range of temperatures. A current control circuit provides means to provide a constant current to an array of current mirror pixel drive elements. The current control circuit comprises a thermally stable bias resistor and a thermally stable band-gap voltage source to provide thermally stable controls and a large L p-channel reference current FET with an associated large L n-channel bias FET configured to provide a reference current at a required voltage to the gate of a large L p-channel current source FET. The current control circuit and the current mirror pixel drive elements are similar circuits with one current control circuit able to control a substantial number of pixel drive elements.

Backplane adaptable to drive emissive pixel arrays of differing pitches

A display system comprising a plurality of display controller circuits controlling a like number of independent segments of pixel drive circuits of a backplane. Each pixel drive circuit comprises a memory element and associated pixel drive circuitry. The segments of the backplane may be organized vertically. The word line for the memory cells of a first segment of pixel drive circuits passes underneath a second segment of pixel drive circuits without directly interacting with the pixel drive circuits of the second segment in order to reach the pixel drive circuits of the first segment. The plurality of display controller circuits operate asynchronously but are kept at the same frame rate by an external signal such as Vsync.

Larger backplane suitable for high speed applications

A backplane operative to drive an array of emissive elements forming a part of a display or display like manufacturing device is disclosed. Each emissive element is mounted to a common pad supplied with current from a plurality of pixel drive elements, wherein each pixel drive element is controlled by a resident memory cell. The plurality of pixel drive elements is organized into a block similar to other blocks of pixel drive elements across the array. The common pad may be driven by a larger or lesser number of pixel drive elements than are present in a single block of pixel drive elements. If not needed, specific pixel drive elements present in a single block may be disabled through a mask change.

A backplane operative to drive an array of emissive pixel elements is disclosed. Each pixel element comprises a pixel circuit drive element and an emissive element, wherein the pixel circuit drive element comprises a memory cell, a current source element, and a modulation element. The present invention improves on an emissive display by providing a backplane and modulation system that enables fabrication of multi-color or monochrome LED display systems that operate efficiently and without objectionable image artifacts. One aspect of the present invention is to realize the backplane in a single crystal silicon process with a minimum number of metal layers while providing each color with a suitable operating voltage and drive current.

Backplane suitable to form part of an emissive pixel array and system and methods of modulating same

Techniques are disclosed for performing topologically planar routing of System in Packages (SiPs). A routing graph can be represented by a particle-insertion-based constraint Delaunay triangulation (PCDT) and its dual. A dynamic search routing may be performed using a DS* routing algorithm to determine the shortest path on the dual graph between a start point and an end point. Based on a dynamic pushing technique, net ordering problems may be solved. A first wire can be topologically routed. Dynamic search routing of a second wire may be performed. The first wire may be pushed or detoured in response to the dynamic searching routing of a second wire.

Growing community of inventors

Los Altos, CA, United States of America

Kaushik Sheth