Micro Technology, Inc.

Mti Technology Corporation

MIT Technology Corp.

Kaushik S Shah

Joseph S Glider

Edward E Asato

Duc H Trang

Kumar Gajjar

Hoke S Johnson, Iii

Chris W Eidler

A block transfer data bus having two separate paths, with each element coupled to the bus having the ability to arbitrate for use of one or the other or both of the bus halves. Each bus half includes an address/data bus portion for sending/receiving the data and addresses. A separate control bus portion for each bus half provides certain status signals and a code indicating the type of data on the address/data bus. An arbitration bus provides data request signals from each element to a central arbiter. In addition, a separate grant signal associated with each bus half is provided back to each element from the arbiter along the arbitration bus. A line on each control signal bus indicates whether or not the bus half is busy.

Dual channel data block transfer bus

An improved interface system based in part on the SCSI standard is provided. A single cable data bus simultaneously transfers several bytes of information between two devices. The interface system transfers multiple-byte commands, messages, status information or data in a single parallel transfer. A microsequencer is provided to permit data transfers across the interface without requiring burdensome attention from a processor in a device involved in the transfer.

Method and apparatus for an enhanced computer system interface

A method and apparatus for transferring data from one device interface to another device interface via elements of a staging memory and a direct memory access (DMA) channel.

Method and apparatus for transferring data through a staging memory

Enhanced interface permitting multiple-byte parallel transfers of

A memory system having multiple memories and multiple ports. Multiplexing logic couples each of the ports to each of the memories. A sequencing circuit controls the multiplexers so that each port is sequentially coupled to each of the memories in sequence in a repeating cycle. When coupled to each memory, a block of data is transferred. A second port is coupled to a different memory at each point in time, with the two ports being switched simultaneously to avoid overlap. A port desiring access to the system must wait until it can fit into this switching queue so that it can transfer in lock-step with the other ports to a different memory. Each port has a data I/O bus, an address input bus, an address counter and R/W controls.

Growing community of inventors

Santa Clara, CA, United States of America

Kaushik S Shah