Purdue Research Foundation

Texas Instruments Corporation

International Business Machines Corporation

Intel Corporation

Kaushik Roy

Hamid Mahmoodi

Akhilesh Ramlaut Jaiswal

Byunghoo Jung

Jae-Joon Kim

Anand Raghunathan

Amogh Agrawal

Ashish Ranjan

Mrigank Sharad

Saibal Mukhopadhyay

Swarup Bhunia

Rajiv V Joshi

Ching-Te Kent Chuang

Jaydeep P Kulkarni

Swagath Venkataramani

Sharat C Prasad

Abhronil Sengupta

Indranil Chakraborty

Zubair Al Azim

Rangharajan Venkatesan

Xuanyao Kelvin Fong

Chamika Mihiranga Liyanagedera

Chao Lu

Qikai Chen

Zoha Pajouhi

Vivek K De

Ali Keshavarzi

Junji Sugisawa

Shubham Jain

Ankit Sharma

Vijay Raghunathan

Dongsoo Lee

Aayush Ankit

Nilanjan Banerjee

Hyung-il Kim

Arijit Raychowhury

Mustafa Ali

Dinesh Somasekhar

Sudip K Nag

Mustafa Fayez Ahmed Ali

Yusung Kim

Sri Harsha Choday

Chih-Hsiang Ho

Utkarsh Saxena

Debabrata Mohapatra

Sang Phill Park

Keejong Kim

A system may include a non-intrusive sensor circuitry configured to provide electrical measurement data, including, for example, current data, voltage data, power factor data, active power consumption data, reactive power consumption data, or a combination thereof. A transient event detector may sweep the electrical measurement data with a first window and a second window, the first window adjacent to the second window. The transient event detector may identify a start and end of transient activity based on electrical measurement data referenced by separate adjacent windows. The transient event detector may capture a transient activity data segment comprising a portion of the electrical measurement data between first index and the second index.

Intelligent non-intrusive load monitoring system

System and methods for high accuracy, non-intrusive current sensing are provided. A system may include two magnetic field sensors configured for differential sensing. The system may further include frontend circuitry configured to remove direct current (DC) offset of the magnetic field sensors, upconvert the outputs of the magnetic field sensors, and filter out at least one frequency component from the up-converted signals. The system may receive output signals from the front-end circuitry corresponding to each sensor. The system may further calculate a differential signal based on the output signals. The system may apply optimal detection based on the differential signal and a reference signal to calculate a measurement of current flow. The system may determine a phase angle measurement between the differential signal and the reference signal to calculate a direction of the current flow in the conductor and output various measurement information related to the detected current.

High accuracy non-invasive current sensor system

An electronic neuron device that includes a thresholding unit which utilizes current-induced spin-orbit torque (SOT). A two-step switching scheme is implemented with the device. In the first step, a charge current through heavy metal (HM) places the magnetization of a nano-magnet along the hard-axis (i.e. an unstable point for the magnet). In the second step, the device receives a current (from an electronic synapse) which moves the magnetization from the unstable point to one of the two stable states. The polarity of the net synaptic current determines the final orientation of the magnetization. A resistive crossbar array may also be provided which functions as the synapse generating a bipolar current that is a weighted sum of the inputs of the device.

Spin orbit torque based electronic neuron

An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (C), and two consecutive bits for carry-out-bar (), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.

In-memory bit-serial addition system

A method of sensing a current in a conductor includes controlling a digital to analog converter output to cancel residual offset voltage in a magnetic tunnel junction device prior to sensing the current with the magnetic tunnel junction device. The method includes switching input to the magnetic tunnel junction device between a fixed voltage and an output of a digital to analog converter while switching input to a band pass filter between a lower and an upper voltage output of the magnetic tunnel junction device. The output of the digital to analog converter is modified to provide a low-amplitude unsaturated sine-wave at an output of the band pass filter, at which point changes in the output of the band pass filter are associated with the amount of current in a sensed conductor.

Vehicle battery current sensing system

Sparsity-aware reconfiguration compute-in-memory (CIM) static random access memory (SRAM) systems are disclosed. In one aspect, a reconfigurable precision succession approximation register (SAR) analog-to-digital converter (ADC) that has the ability to form (n+m) bit precision using n-bit and m-bit sub-ADCs is provided. By controlling which sub-ADCs are used based on data sparsity, precision may be maintained as needed while providing a more energy efficient design.

Sparsity-aware reconfigurable compute-in-memory (CIM) static random access memory (SRAM)

A current sensing system, comprising at least one magnetic tunnel junction device placed adjacent to a current carrying conductor electrically connected to a battery of a vehicle. The magnetic tunnel junction device is configured to measure a magnetic field around the conductor. A monitoring device is operatively connected to the magnetic tunnel junction device, wherein the monitoring device is configured to receive the magnetic field measurement and determine an estimate of the current flowing through the conductor.

An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

Approximate cache memory

A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors Tand T, where Tis controlled by the value held in the associated memory cell and Tis controlled by a row-dedicated source (v) for each row, the combination of the Tand Ttransistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2, . . . Rmax, where Rmax is the resistance of the least significant cell in each row.

Multi-bit dot product engine

An in-situ in-memory implication gate is disclosed. The gate include a memory cell. The cell includes a first voltage source, a second voltage source lower in value than the first voltage source, a first and second magnetic tunneling junction devices (MTJ) selectively juxtaposed in a series and mirror imaged relationship between the first and second sources, each having a pinned layer (PL) in a first direction and a free layer (FL) having a polarity that can be switched from the first direction in which case the MTJ is in a parallel configuration presenting an electrical resistance to current flow below a first resistance threshold to a second direction in which case the MTJ is in an anti-parallel configuration presenting an electrical resistance to current flow higher than a second resistance threshold, and further each having a non-magnetic layer (NML) separating the PL from the FL.

Memory device having in-situ in-memory stateful vector logic operation

A bit cell driving mechanism is disclosed. The mechanism includes a bit cell which includes a first magnetic tunnel junction (MTJ) cell, including a pinned layer, a non-magnetic layer, a free layer having two magnetic regions separated by a laterally moveable domain wall, and a spin-hall metal layer configured to receive an electrical current therethrough which causes the DW to move laterally. The mechanism also includes a second MTJ cell coupled to the first MTJ cell as well as an interconnect driver configured to provide electrical current to the first MTJ cell during a write operation.

Buffered spin-torque sensing device for global interconnect circuits

An electronic synapse is disclosed, comprising a heavy metal layer having a high spin orbit coupling, a domain wall magnet layer having a bottom surface adjacent to a top surface of the heavy metal layer, the domain wall magnet layer having a perpendicular magnetic anisotropy, the domain wall magnet layer having a domain wall, the domain wall running parallel to a longitudinal axis of the domain wall magnet layer, a pinned layer having perpendicular magnetic anisotropy, and an oxide tunnel barrier connected between the domain wall magnet layer and the pinned layer, wherein the pinned layer, the oxide tunnel barrier, and the free layer form a magnetic tunnel junction.

Electronic synapse having spin-orbit torque induced spike-timing dependent plasticity

An electronic comparison system includes input stages that successively provide bits of code words. One-shots connected to respective stages successively provide a first bit value until receiving a bit having a non-preferred value concurrently with an enable signal, and then provide a second, different bit value. An enable circuit provides the enable signal if at least one of the one-shots is providing the first bit value. A neural network system includes a crossbar with row and column electrodes and resistive memory elements at their intersections. A writing circuit stores weights in the elements. A signal source applies signals to the row electrodes. Comparators compare signals on the column electrodes to corresponding references using domain-wall neurons and store bit values in CMOS latches by comparison with a threshold.

Electronic comparison systems

Growing community of inventors

West Lafayette, IN, United States of America

Kaushik Roy