National Instruments Corporation

Cadence Design Systems, Inc.

Kaushik Ravindran

Jacob Kornerup

Guang Yu Yang

Jeffrey N Correll

Rhishikesh Limaye

Guoqiang Wang

Arkadeb Ghosal

Michael J Trimborn

Hugo A Andrade

Sadia B Malik

Charles E Crain, Ii

Ian C Wong

Trung N Tran

Newton G Petersen

Andreas Kuehlmann

Ellen Sentovich

John R Allen

Ankita Prasad

Patricia Derler

Charles E Crain Ii

Guang Yang

A method for determining timing constraints in dataflow models is disclosed. The method includes receiving node information specifying a plurality of dataflow nodes, as well as coupling between various ones of the dataflow nodes. The method further comprising receiving timing information specifying timing constraints for at least some of the dataflow nodes. Based on the node information, the couplings between the nodes, and the timing information, a timeline dependency graph (TDG). The timeline dependency graph illustrates a timeline, mappings between nodes with side effects to firing times of those nodes on the timeline, and dependencies between nodes.

Determination of timing configurations for program dataflow models

Techniques for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and specifications or constraints for the graphical program or at least one of the functional blocks in the graphical program. The specified model of computation and specifications or constraints are useable to analyze the graphical program or generate a program or simulation.

Graphical specification and constraint language for developing programs for hardware implementation and use

System and method for specifying and implementing programs. A graphical program is created in a graphical specification and constraint language that allows specification of a model of computation and explicit declaration of constraints in response to user input. The graphical program includes a specified model of computation, a plurality of interconnected functional blocks that visually indicate functionality of the graphical program in accordance with the specified model of computation, and specifications or constraints for the graphical program or at least one of the functional blocks in the graphical program. The specified model of computation and specifications or constraints are useable to analyze the graphical program or generate a program or simulation.

System and method for optimizing a data flow diagram based on access pattern information are described. Access pattern information for a data flow diagram may be received. The data flow diagram may include a plurality of interconnected actors, e.g., functional blocks, visually indicating functionality of the data flow diagram. The access pattern information may include one or more of: input pattern information specifying cycles on which tokens are consumed by at least one of the actors, or output pattern information specifying cycles on which tokens are produced by at least one of the actors. A program that implements the functionality of the data flow diagram may be generated based at least in part on the access pattern information.

Optimization of a data flow program based on access pattern information

Developing programs for hardware implementation in a graphical specification and constraint language

Developing programs in a graphical specification and constraint language

Developing programs for hardware implementation in a graphical specification and constraint language Via iterative estimation of performance or resource utilization

The present invention provides a process for constrained clock skew scheduling which computes for a given number of clocking domains the optimal phase shifts for the domains and the assignment of the individual registers to the domains. For the within domain latency values, the algorithm can assume a zero-skew clock delivery or apply a user-provided upper bound. Experiments have demonstrated that a constrained clock skew schedule using a few clocking domains combined with small within-domain latency can reliably implement the full sequential optimization potential to date only possible with an unconstrained clock schedule.

Multi-domain clock skew scheduling

Growing community of inventors

Berkeley, CA, United States of America

Kaushik Ravindran