Cirrus Logic Inc.

Broadcom Corporation

Synopsys, Inc.

Alacritech, Inc.

Gazelle Microcircuits, Inc.

Kaushik L Popat

Balaji Venugopal Virajpet

Siamack Nemazie

William R Foland, Jr

Shiang-Jyh Chang

Roger McPherson

Vineet Dujari

Maoxin Wei

Millind Mittal

Stephen A Smith

Bryan Michael Richter

Vineet Gupta

Amod Bodas

Tarun Kumar Tripathy

David C MacMillan

David Sherman

Fukuji Sugie

William Ip

Martin Kite

A memory management unit (MMU) is disclosed for storing mappings between virtual addresses and physical addresses. The MMU includes a translation look-aside buffer (TLB) and a memory management unit controller. The TLB stores mappings between a virtual address and a physical address. The MMU controller receives a request to insert an entry into the TLB and performs a set of operations based on the received request. The MMU controller determines whether an entry stored in the TLB is associated with the virtual address of the request, removes the entry stored in the TLB that is associated with the virtual address and inserts the requested entry into the TLB.

Method and processor for reducing code and latency of TLB maintenance operations in a configurable processor

An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.

Systems and methods for data storage devices and controllers

Mixed-signal single-chip integrated system electronics for data storage devices

Integrated disc drive controller

A copy instruction executed by a functional-level instruction-set computing (FLIC) processor copies a variable-length data block from one resource to another resource through a cross-bar switch. Resources include general-purpose registers, input, output, and execution buffers, DRAM, SRAM, and other memory. A copy-with-validate instruction has an operand pointing to a first rule in an immediate rule table. The first rule controls validation of a first data-item in the data being copied. Validation includes range and equality checking of the data-item. The value of the data-item or the current offset can be written to a register. A format field in the rule indicates the size of the data-item, or the size is read from the data-item for variable-size formats. The current offset is incremented by the size. The next data-item is validated by a next rule, and other rules in the immediate table control validation of other data-items in the data block.

Native copy instruction for file-access processor with copy-rule-based validation

A method and apparatus are described which allow for greater control of interrupt generation to a processor or the like. In one embodiment, a priority selection device is provided which allows a processor or other devices to set the relative priorities among different interrupt requests. The priority information may be dynamic in that it can be modified at other times (e.g., based on the needs of the computer system). A priority resolution device and mask logic device determine which of the generated interrupt requests is of the highest priority and generates an interrupt to the processor to service that high-priority interrupt. In one embodiment, when a processor is servicing an interrupt and a higher priority interrupt is generated, the processor nests the servicing of the higher-priority interrupt in the servicing of the current interrupt. If the newly asserted interrupt request has a priority that is less than the priority of the currently serviced interrupt, the lower-priority interrupt is prevented from being asserted to the processor (until at least the servicing of the higher-priority interrupt is complete, for example).

Method and apparatus for controlling interrupt priority resolution

A memory map for a computer system is configurable. For example a first section of the memory map (e.g., the lower address space) is configurable so that when the process accesses this section, different devices will respond depending on the memory map in effect. In one embodiment, external non-volatile memory is accessed during a first time period based on a reset memory map. After initialization, the memory may is changed to a normal one so that subsequent accesses to the same section of the memory map result in accesses to faster memory (e.g., internal SRAM). In the case where the reset vector and interrupt vectors have relatively close addresses, the configurability of the memory map allows the reset vector to be handled through accesses to non-volatile memory while interrupt vectors are handled through accesses to faster internal SRAM.

Configurable system memory map

A FIFO is operated so no changes occur on an output thereof in response to (1) only one stage of the FIFO having a signal stored therein when a read command is supplied to the FIFO exclusively of a write command and/or (2) the FIFO being flushed, i.e., erased. Result (1) is achieved by decrementing a write pointer by one without changing a read pointer or by loading the write pointer with the contents of the read pointer. Result (2) is achieved by loading the write pointer with the contents of the read pointer.

FIFO and method of operating same which inhibits output transitions when the last cell is read or when the FIFO is erased

An integrated HDD system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g. digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. The invention takes advantage of existing circuit design modules provided in the integrated circuit as &ldquo;hard block&rdquo; components which are unchanged by integrated circuit design software. Changes in operability of the overall integrated circuit may be readily achieved by altering &ldquo;soft block&rdquo; components to customize or tailor the design for a particular hard drive. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components.

Mixed-signal single-chip integrated system electronics for magnetic hard disk drives

A wired combinational logic arrangement responsive to N binary signal sources includes N circuits, one for each source. The circuits drive a common output terminal. Each circuit includes first and second devices for pulling the common terminal to first and second different voltages during successive abutting activation periods. The first device supplies a current to the common terminal that is considerably greater than the current supplied to the common terminal by the second device. The arrangement further includes a third device for pulling the common terminal to the second voltage at all times. The third device supplies a current to the common terminal that is either equal to or less than the current supplied by the second device.

Wired combinational logic circuit with pullup and pulldown devices

A method and apparatus for arbitration among users for a resource has a single shared user request line over which each of the users asserts request signals for use of the resource. Dynamic priority assignment is provided, in which the sequence of users is changed as a function of the last user to use the resource. A time multiplexed format for arbitration is followed, with each user keeping track of which user's turn it is to request use of the resource. This prevents starvation of an individual user and allows great flexibility in assigning priority to the users, while reducing pin counts and signal traces.

Arrangement and method of arbitration for a resource with shared user

A computer system is provided with a central processing unit (CPU), a bus master coupled to the CPU, and a plurality of interface cards that interface the computer system with peripheral devices. A plurality of host adapters are coupled between the bus master and the interface cards. The host adapters adapt signals between the CPU and the interface cards. Each host adapter generates a ready signal that when asserted indicates readiness of the host adapter to receive address information from the bus master and have data information read by the bus master. An address/data bus is coupled between the bus master and the host adapters. A single separate ready line is coupled between each of the host adapters and the bus master, each ready line carrying the ready signal from a different one of the host adapters to the bus master. The single ready signal carried by a single line serves both an address ready and a data ready signalling function, to thereby, reduce the pin count in the host adapter serving as a slave.

Method and an arrangement for handshaking on a bus to transfer

Voltage pullup or pulldown devices of general purpose input/output pads of integrated circuit chips are controlled by signals derived from a core of the chip and which indicate (1) if the pad is to be enabled to output a value and (2) the value of the signal to be outputted. Such devices are controlled to supply different current levels to the input/output terminals as a function of whether the chip is operating in 'sleep' and interrupt modes. The device of each pad is disabled when signals or commands are supplied via the pad from the chip to circuitry external to the chip and vice versa.

Integrated circuit with input/output pad having pullup or pulldown

A delay circit is described which automatically adjusts the propagation delay of clock signals, generated by a clock source, distributed to various receiving devices so that the receiving devices are clocked simultaneously. In one embodiment, the clock signal generated by a single clock source is independently delayed for each receiving device. To determine the proper amount of delay, a clock signal is simultaneously transmitted to each of the receiving devices and a clock return signal from each receiving device is returned to a delay circuit via a return path. The delay circuit detects the various differences in round-trip arrival times of the clock signal associated with each receiving device and fixes a particular clock signal delay for each receiving device so that subsequent clock signals will arrive at each receiving device simultaneoulsy.

Growing community of inventors

Pleasanton, CA, United States of America

Kaushik L Popat