Netlogic Microsystems, Inc

Broadcom Corporation

Kaushik Kuila

David T Hass

Ahmed Shahid

Gaurav Garg

Gaurav Singh

Robert Laker

Ozair Usmani

An apparatus and method are provided for allocating a plurality of packets to different processor threads. In operation, a plurality of packets are parsed to gather packet information. Additionally, a parse operation is performed utilizing the packet information to generate a key, and a hash algorithm is performed on this key to produce a hash. Further, the packets are allocated to different processor threads, utilizing the hash or the key.

System and method for parsing and allocating a plurality of packets to processor core threads

Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers.

Programmable micro-core processors for packet parsing

A system, method, and computer program product are provided for saving and restoring a compression-decompression state. In operation, data is processed, the processing including compressing or decompressing the data. Additionally, a state of the processing is saved. Further, the state of the processing is restored.

System, method, and computer program product for saving and restoring a compression/decompression state

Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers. A dependency list is used to maintain proper ordering of packets being processed by the micro-cores.

Programmable micro-core processors for packet parsing with packet ordering

Systems, apparatusses, and methods are disclosed for transmission control protocol (TCP) segmentation offload (TSO). A hardware TSO engine is capable of handling segmentation of data packets and consequent header field mutation of hundreds of flows simultaneously. The TSO engine generates data pointers in order to 'cut up' the payload data of a data packet, thereby creating multiple TCP segments. Once the data of the data packet has been fetched, the TSO engine 'packs' the potentially-scattered chunks of data into TCP segments, and recalculates each TCP segment's internet protocol (IP) length, IP identification (ID), IP checksum, TCP sequence number, and TCP checksum, as well as modifies the TCP flags. The TSO engine is able to rapidly switch contexts, and share the control logic amongst all flows.

TCP segmentation offload (TSO) using a hybrid approach of manipulating memory pointers and actual packet data

A method and system of packet assembly is provided. The method includes providing a first packet descriptor. The first packet descriptor is a pointer-to-pointer (P2P) descriptor that includes pointer information. The method further includes retrieving a first pointer referenced by the pointer information of the first packet descriptor; providing the first pointer to a DMA engine; and using the DMA engine to retrieve packet data referenced by the first pointer.

System and method for offloading packet protocol encapsulation from software

A network-on-chip system, method, and computer program product are provided for transmitting messages utilizing a centralized on-chip shared memory switch. In operation, a message is sent from one of a plurality of agents connected on a messaging network. The message is received at a central shared memory switch, the central shared memory switch being in communication with each of the plurality of agents. Further, the message is transmitted from the central shared memory switch to a destination agent, the destination agent being one of the plurality of agents.

Network-on-chip system, method, and computer program product for transmitting messages utilizing a centralized on-chip shared memory switch

A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.

System and method for reducing latency associated with timestamps in a multi-core, multi-threaded processor

A method is provided for offloading packet protocol encapsulation from software. In operation, pointer information is received. Furthermore, packet protocol encapsulation is offloaded from software by assembling packets in hardware, using the pointer information.

Growing community of inventors

San Jose, CA, United States of America

Kaushik Kuila