Intel Corporation

Amazon Technologies, Inc.

Kaushik Dasgupta

Chintan S Thakkar

Anandaroop Chakrabarti

Kameran Azadet

Shilpa Talwar

Hosein Nikopour

Bryan K Casper

Ofir Degani

Wook Bong Lee

Ashoke Ravi

Michael Genossar

Claudio Da Silva

Stefano Pellerano

Debabani Choudhury

Rotem Banin

Albert Molina

Sidharth Dalmia

Georgios Yorgos Palaskas

Igal Kushnir

Duncan Kitchin

Saku Lahti

Oner Orhan

Emanuel Cohen

Mikko S Komulainen

Gadi Shor

Chuanzhao Yu

Jayprakash Thakur

Eren Sasoglu

Arnaud Lucres Amadjikpe

Menashe Soffer

Kunal Datta

Ana M Yepes

Run Levinger

Moshe Teplitsky

Omer Asaf

Eshel Gordon

Erkan Alpman

Nebil Tanzi

Josef Hagn

Ron Pongratz

Tawfiq Musah

Baljit Singh

Peter Sagazio

Amit Freiman

Eyal Goldberger

Eran Gerson

Shmuel Ravid

Shuhei Yamada

Hyun Yoon

Yossi Tsfati

Resti Montoya Moreno

Nir Weisman

Noam Kogan

Marian K Verhelst

Meir Gordon

Mikko M Lampinen

Miroslav Baryakh

Naftali Landsberg

Ra'anan Sover

Stefan Shopov

Lior Shakedd

Avi Tsarfati

Saeid Daneshgar Asl

Amr M Fahim

Shinwon Kang

Te Yu Kao

Nathan G Narevsky

Anat Bazov

Saeid Daneshgar

Stefano Brenna

Gregory Chance

Xi Li

Brandon Davis

Gregory W Chance

Brandon R Davis

Sunny Sharma

An on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

Millimeter wave transmitter design

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

Wireless communication technology, apparatuses, and methods

Technologies directed to binning methods for electronically steered transmit phased arrays with amplitude tapering are described. One communication system includes a first and a second set of power amplifiers. The first set operates with a first peak power level and the second set operates with a second peak power level that is lower than the first peak power level. A digital beamforming (DBF) device sends a first set of signals to the first set of power amplifiers causing the first set of power amplifiers to operate in a first range. The DBF also sends a second set of signals to the second set of power amplifiers causing the second set of power amplifiers to operate in a second range.

Power amplifier binning method for electronically steered phased array antennas with amplitude tapering

Growing community of inventors

Hillsboro, OR, United States of America

Kaushik Dasgupta