International Business Machines Corporation

Altera Corporation

Other

Advanced Micro Devices Corporation

Globalfoundries Inc.

Rensselaer Polytechnic Institute

Auriga Innovations, Inc

Kaushik Chanda

Ronald G Filippi

Andrew Herbert Simon

Chih-Chao Yang

Ping-Chuan Wang

Griselda Bonilla

Stephan Grunow

Naftali Eliahu Lustig

Lawrence Alfred Clevenger

Samuel S Choi

Daniel C Edelstein

Baozhen Li

Andrew P Cowley

Theodorus E Standaert

Paul Stephen McLaughlin

Sujatha Sankaran

Jason Paul Gill

Junjing Bao

Yun-Yu Wang

Hazara Singh Rathore

Timothy Dooling Sullivan

Tom C Lee

James J Demarest

Chao-Kun Hu

Lynne Marie Gignac

Du Binh Nguyen

Roy Charles Iggulden

Birendra N Agarwala

Robert Daniel Edwards

Shom Ponoth

Son Van Nguyen

Wai-Kin Li

Hosadurga K Shobha

Satyanarayana Venkata Nitta

Shyng-Tsong Chen

Edward William Kiewra

Dan Moy

Cathryn Jeanne Christiansen

Joseph M Lukaitis

Vadali Mahadev

Jeffrey P Gambino

Yun Yu Wang

Timothy Joseph Dalton

Mahesh A Iyer

Arifur Rahman

Terry Allen Spooner

Kyung Suk Oh

Vincent James McGahay

David Lee Rath

Stephen Edward Greco

Ravi Prakash Gutala

Sunfei Fang

Hui Liu

Louis L C Hsu

Daewon Yang

Larry Clevenger

Andy Cowley

Charles C Goldsmith

Tibor Bolom

Shyam P Murarka

Karthik Chandrasekar

Archanna Srinivasan

Conrad A Barile

Ramanath Ganapathiraman

Samuel Sung Shik Choi

James D Werking

Ahila Krishnamoorthy

Gurvinder Tiwana

Ronald M Beach

Ganesh Sure

Rajiv Mongia

Srikanth Darbha

Wai-Kin Ll

Ping-Chaun Wang

Edward W Kiewara

Chih-Chao Ibm United Kingdom Limited Yang

Systems and methods are provided for generating a circuit design for an integrated circuit using a circuit design tool. The circuit design tool determines maximum junction temperatures for circuit blocks in the circuit design for the integrated circuit. The circuit design tool determines defects values for the circuit blocks using the maximum junction temperatures for the circuit blocks. The circuit design tool determines a defects value for the circuit design based on the defects values for the circuit blocks. The circuit design tool determines a maximum junction temperature for the circuit design based on a comparison between the defects value for the circuit design and a target defects value for the circuit design. The circuit design tool can dynamically reconfigure configurable logic circuit blocks to improve the power, the performance, and the thermal profile to achieve an optimal junction temperature per circuit block.

Systems and methods for circuit design dependent programmable maximum junction temperatures

A back end of the line (BEOL) fuse structure having a stack of vias. The stacking of vias leads to high aspect ratios making liner and seed coverage inside the vias poorer. The weakness of the liner and seed layers leads to a higher probability of electromigration (EM) failure. The fuse structure addresses failures due to poor liner and seed coverage. Design features permit determining where failures occur, determining the extent of the damaged region after fuse programming and preventing further propagation of the damaged dielectric region.

Stacked via structure for metal fuse applications

A test system for testing an integrated circuit package is provided. The test system may include a test board on which a package under test can be mounted, a test box for gathering desired measurements on the package under test, and a test host for automatically controlling the test box during testing. The test box may be coupled to row multiplexing circuitry and column multiplexing circuitry for selectively addressing one or more daisy-chained nets in the package under test. The test box may also be coupled to a source measurement unit (SMU) component that provides current source signals to the package under test and to a digital multimeter (DMM) component that provides voltage sense signals to the package under test. Arranged in this way, the test system can be configured to perform automated I-V curve tracing, resistance measurements, open/short circuit detection, and monitoring of other package-level manufacturing defects.

Methods and apparatus for automated integrated circuit package testing

Circuitry having power lines with comparable path resistances may include input-output blocks in an integrated circuit (IC) that are coupled to respective sets of bumps on the IC. The circuitry may have a core region and a periphery region. Groups of input-output blocks may be formed in the periphery region. A first set of power lines in the circuitry extends from the core region to the first group of input-output blocks whereas a second set of power lines in the circuitry extends from the core region to the second group of input-output blocks. The first and second sets of power lines are physically separate from each other.

Power line layout in integrated circuits

A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Back-end electrically programmable fuse

An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided.

Interconnect structure with enhanced reliability

Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.

Metal fuse structure for improved programming capability

E-fuse structures in back end of the line (BEOL) interconnects and methods of manufacture are provided. The method includes forming an interconnect via in a substrate in alignment with a first underlying metal wire and forming an e-fuse via in the substrate, exposing a second underlying metal wire. The method further includes forming a defect with the second underlying metal wire and filling the interconnect via with metal and in contact with the first underlying metal wire thereby forming an interconnect structure. The method further includes filling the e-fuse via with the metal and in contact with the defect and the second underlying metal wire thereby forming an e-fuse structure.

E-fuse structures and methods of manufacture

A metal fuse structure using redundant vias formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes a first dielectric layer having a conductor, a second dielectric layer above the first dielectric layer having a first conductive line and a first via, the first via is on the conductor, the first conductive line is on the first via, the first via is the only electrical connection between the first conductive line and the conductor, and a third dielectric layer above the second dielectric layer having a second conductive line, a second via and a third via, the second via and the third via are both on the first conductive line, the second conductive line is on both the first via and the second via.

Redundant via structure for metal fuse applications

An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

System involving electrically reprogrammable fuses

Growing community of inventors

Fishkill, NY, United States of America

Kaushik Chanda