Qualcomm Incorporated

Conduent Business Services, LLC

Kaushik Baruah

Narayanan Unny Edakunni

Thomas Hua-Min Williams

A MOS IC includes a first circuit including a first plurality of nMOS devices, a first p-tap cell, and a first dummy nMOS cell, and a second circuit including a first plurality of pMOS devices, a first dummy pMOS cell, and a first n-tap cell. The nMOS/pMOS devices are spaced apart in a first direction. The first p-tap cell and the first dummy nMOS cell are adjacent to each other in the first direction between the nMOS devices. The first dummy pMOS cell and the first n-tap cell are adjacent to each other in the first direction between the pMOS devices. The pMOS devices are adjacent to the nMOS devices in a second direction orthogonal to the first direction. The first p-tap cell/the first dummy pMOS cell and the first dummy nMOS cell/the first n-tap cell are respectively adjacent to each other in the second direction.

Dummy cell and tap cell layout structure

Systems and methods for allocating resources in a transportation system are disclosed. A vehicle of the transportation system may be dispatched by one or more processors; first and second portions of the vehicle are allocated to first and second groups of users. A parameter of the first group of users may be tracked at a first location. Part of the second portion of the vehicle may be reallocated to the first group of users, in real-time, when the tracked parameter of the first group of users exceeds a threshold.

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Bengaluru, India

Kaushik Baruah