Xilinx, Inc.

Hellosoft, Inc.

Imagination Technologies Limited

Hellosoft India Pvt. Ltd

Kaushik Barman

Raghavendra Malladi

Allan A Johnson

Luis Aldaz

Parag Dighe

Luis Aldaz, Sr, Legal Representative

Sriram Kankipati

Luis Aldaz, Jr

Shail Aditya Gupta

Baris Ozgul

Raghavendar Mysore Rao

Gregory C Copeland

Sarvendra Govindammagari

Sneha Bhalchandra Date

Samuel R Bayliss

Dinesh K Monga

Heramba Aligave

Krushna Prasad Ojha

Vellenki Umapathi Reddy

Vellenki Umapathy Reddy

Ragahavendar M Rao

Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bitstream and/or binary code which configures programmable and non-programmable logic in a heterogeneous processing environment of a SoC to execute the graph. The compiler can also consider user-defined constraints when compiling the source code. The constraints can dictate where the kernels and buffers should be placed in the heterogeneous processing environment, performance requirements, data communication routes through the SoC, type of data path, delays, and the like.

Constraints for applications in a heterogeneous programming environment

Techniques related to a data processing engine for an integrated circuit (IC) are described. In an example, a method is provided for vectorized peak detection. The method includes dividing a set of data samples of a data signal, corresponding to a peak detection window (PDW), into a plurality of subsets of data samples each comprising a number of data samples. The method includes performing vector operations on each of the plurality of subsets of data samples. The method includes determining a running index of a sample with a maximum amplitude over the PDW based on the vector operations.

Vectorized peak detection for signal processing

Conditional activation and deactivation of a microprocessor. A hardware portion of an apparatus performs packet processing on received data, where the hardware portion selectively decodes the received data. A microprocessor performs data processing on decoded data, where the microprocessor is conditionally activated for performing the data processing and is conditionally deactivated when not performing the data processing. An output portion receives processed data and audibly renders the processed data without requiring the microprocessor.

Conditional activation and deactivation of a microprocessor

A method relates generally to data transmission. In such a method, a peak detector detects a signal peak of an input signal exceeding a threshold amplitude. This detecting includes sampling the input signal at a sampling frequency to provide a sampled signal. The sampling frequency is in a range greater than a bandwidth frequency of a carrier signal used for providing the input signal and less than twice the bandwidth frequency. Samples of the sampled signal proximate to the signal peak are interpolated to provide a reconstructed peak. A cancellation pulse is applied by a cancellation pulse generator to the samples to reduce the signal peak. A version of the input signal is output after application of the cancellation pulse.

Pulse cancellation crest factor reduction with a low sampling rate

A battery-powered WLAN communication device has an activity sensor operable to identify an available packet. A PHY module is awakened to begin receiving the packet. The PHY module decodes a full MAC address from a MAC portion of a header of the packet. A MAC address parser receives the MAC address and determines whether the packet is to be received by comparing the full MAC address to a MAC address of the WLAN communication device. The MAC address parser is awakened to perform the comparing and shutdown after. Packets to be received include beacon packets. A hardware centric MAC separate from the MAC address parser has a beacon processor capable of being awakened from a shutdown state to process a beacon packet. The PHY module, the MAC address parser, and the beacon processor module are operable to be awakened and shutdown independently of each other and of a microprocessor.

Hardware-based beacon processing

In one embodiment, a matrix multiplication circuit is provided. The circuit includes a plurality of systolic arrays, a pre-processing circuit, and a post-processing circuit. The pre-processing circuit is configured to receive first and second input matrices, and decompose the first input matrix into a plurality of sub-matrices. The pre-processing circuit inputs each of the plurality of sub-matrices to at least a respective one of the plurality of systolic arrays for multiplication with the second input matrix. The post-processing circuit is configured to combine output of the systolic arrays into a result matrix.

Multiplication of matrices using systolic arrays

An apparatus comprises a network physical layer and an activity sensor for sensing a packet and activating the network physical layer from shutdown. The network physical layer decodes a PHY header portion and a media access control header portion of a packet header. A MAC has a fixed hardware media access plane implementing IEEE 802.11 series MAC functionality and couples to a microprocessor. A MAC address parser receives the MAC header portion of the packet, for processing the MAC header portion of the packet, and for activating the MAC from a shutdown in response to recognizing a MAC address within the MAC header portion of the packet, such that the MAC is not activated if the MAC parser does not recognize the MAC address, wherein the MAC is operable, after activation, to perform MAC functionality without the microprocessor and to provide data from the packet to the microprocessor.

Hardware-based packet address parsing for packet reception in wireless networks

Approaches for Cholesky decomposition of a matrix are described. A first circuit is configured to generate an inverse square root of an input value. A second circuit is configured to generate a product of a value output by the first circuit and provided at a first input and a value provided at a second input. A third circuit is configured to generate a difference between a value provided at the first input and a value provided at the second input of the third circuit. The first input of the third circuit is coupled to the output of the second circuit. A control circuit is configured to iteratively distribute a plurality of values of the matrix and the outputs of the first, second, and third circuits to the inputs of the first, second, and third circuits such that the Cholesky decomposition of the matrix is output by the third circuit.

Circuits and methods for calculating a cholesky decomposition of a matrix

Methods and circuits process a data block of first bits. A circuit includes a register and a parallel combiner. The register is configured to store second bits. The second bits are iteratively a partial parity for each of multiple frames of the data block. The parallel combiner is coupled to the register and configured to generate a combination of bits from third bits and the second bits from the register. These third bits are iteratively those of the first bits within each of the frames of the data block. The circuit also includes respective exclusive-or circuits associated with the second bits. These exclusive-or circuits are coupled to the parallel combiner and the register. The respective exclusive-or circuit for each second bit is configured to generate the second bit from the combination of bits.

Methods and circuits for processing a data block by frames

Passive listening in wireless communication. An activity sensor device senses a packet. A medium access control (MAC) address parser receives the packet, processes a header of the packet, and activates a MAC device in response to recognizing a MAC address within the header, such that the MAC device is not activated if the MAC address parser does not recognize the MAC address.

Passive listening in wireless communication

Hardware-based beacon processing. A hardware-centric medium access control (MAC) device includes a packet receiver and a beacon processor. The packet receiver receives a plurality of packets comprising at least one beacon packet. The beacon processor receives packets of the plurality of packets and filters out unwanted packets of the plurality of packets without requiring the use of other components of the hardware-centric MAC device and without requiring the use of a microprocessor.

A hardware-centric medium access control (MAC) device comprises a control plane module and a hardware media access planed module. The control plane module is configured for providing control functions of the hardware-centric MAC device. The hardware media access plane module communicatively coupled to the control plane module is configured for performing real-time data communication functions without requiring a microprocessor.

Hardware-centric medium access control (MAC) device

A method and system for low-complexity implementation of a Viterbi Decoder with near optimal performance has been disclosed. The Viterbi decoding technique is diagrammatically represented as a trellis. The trellis includes various states at different time instants, and branches connecting these states. Each state has an associated state metric and a survivor path sequence, whereas each branch has a branch metric. The state metric for each current state is checked for crossing a predefined limit. If it crosses the predefined limit, the state metric is updated with a new metric that is obtained by subtracting a constant value from the state metric. Thereafter, the method finds a common path in the trellis at each state and updates the survivor path sequence of each state. The Most Significant Bits (MSBs) of the survivor path sequences of the states at a particular time instant are computed and the original data is decoded, based on the count of '0s' and '1s' in the MSBs.

Low complexity implementation of a Viterbi decoder with near optimal performance

A hardware-centric medium access control (MAC) device comprises a control plane module and a hardware media access planed module. The control plane module is for providing control functions of the hardware-centric MAC device. The hardware media access plane module communicatively coupled to the control plane module is for performing real-time data communication functions without requiring a microprocessor.

A method and apparatus for multi-path channel characterization in a Direct Sequence Spread Spectrum based wireless communication system is provided. The multipath channel is modeled as a tapped delay line FIR filter with L taps corresponding to L paths. A pre-defined training sequence is transmitted over the multipath channel. The received signal is sampled and cross correlations are computed between the samples obtained and the spreading sequence for various time lags to obtain the symbol boundary. Thereafter, a desired set of L cross correlations for L time lags around the symbol boundary is estimated. For this, all the L possible sets of L cross correlations for L time lags around the symbol boundary are considered. The energy in the cross correlations corresponding to each considered set is calculated. The set of L cross correlations having the maximum energy is selected for tap computation. The tap coefficients are estimated by solving a set of L simultaneous linear equations.

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Hyderabad Telangana, India

Kaushik Barman