Atrenta, Inc.

Kaushal Kishore Pathak

Ravi Varadarajan

Jitendra Kumar Gupta

Sanjiv Mathur

Anup Nagrath

Priyank Mittal

Kshitiz Krishna

Lenuta Georgeta Claudia Rusu

Ritesh Mittal

System-on-chip (SoC) designs include large amounts of interconnected intellectual property blocks and standard-cell logic using complex bus fabrics. Today SoC design-closure that validates design targets of area, timing, congestion and power constraints is accomplished post routing as over 80% of validation problems are due to global-interconnect. A method is disclosed that allows the designers to achieve global design-closure and physical topology constraints, early in the design cycle, at much higher levels of abstraction. In particular, logic hierarchy of the design is converted into a physical hierarchy of functional-related clusters of locally-connected logic. The clusters and inter-cluster global connections can be refined to meet design constraints in order to generate a top-level floor-plan in the form of library and constraint files. Using the results of this top-down global design-closure method the designers can use the generated floor-plan to guide downstream tools to achieve predictable and correlatable design implementation.

Method of global design closure at top level and driving of downstream implementation flow

An electronic design automation method implemented in a computing system is provided for creating a physical connections netlist for a pre-floorplan partitioned design file of 3D integrated circuits. The inputs are a 3D stack defining the topology of multiple dies, and a given design partitioning. The design partitioning defines the logic implemented in each die. The method identifies through-silicon-vias (TSVs), bump pins (BPs) and net connections.

Method for creating physical connections in 3D integrated circuits

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Ghaziabad, India

Kaushal Kishore Pathak