International Business Machines Corporation

Kattamuri Ekanadham

Pratap Chandra Pattnaik

Jose Eduardo Moreira

Manoj N Kumar

Mauricio J Serrano

Harold Wade Cain, Iii

Jessica Hui-Chun Tseng

Rudolph N Rechtschaffen

Il Park

David Michael Daly

Joefon Jann

Hao Yu

Gianfranco Bilardi

Ilie G Tanase

William Pettit Horn

Michael Huang

Jessica Tseng

Simone Sbaraglia

Beng-Hong Lim

Derek E Williams

Maged M Michael

Dimitrios Pendarakis

Richard Harold Boivie

William Eric Hall

David R Safford

Kenneth Alan Goldman

Peter Anthony Sandon

Vijay Krishnarao Naik

Bhushan Pradip Jain

Mohit Kapur

Debapriya Chatterjee

Enriquillo Valdez

I-Hsin Chung

Hui-Fang Wen

David Joseph Klepacki

Marc Snir

Chung-Lung K Shum

Dung Q Nguyen

Hung Qui Le

Brian William Thompto

Hubertus Franke

Silvia Melitta Mueller

David S Levitan

Ronald Mraz

Maarten Jakob Boersma

Brian R Konigsburg

Seetharami R Seelam

Douglas James Joseph

Jennifer A Navarro

David Mui

Niels Fricke

Guojing Cong

Sandra Johnson Baylor

Arnold Flores

Robert E Walkup

Guerney Douglass Holloway Hunt

Il Mok Park

Sandhya Koteshwara

Martijn Diede Berkers

Luiz A DeRose

Guerney D Hunt

Manoj Kumar

A data ordering device includes a plurality of inputs N and a plurality of outputs M. There is a sorting network coupled between the plurality of inputs N and the plurality of outputs M. There are one or more latches comprising a buffer coupled between each input of the plurality of inputs N and a corresponding input of the sorting network. There are one or more latches comprising a buffer coupled between each output of the plurality of outputs M and a corresponding output of the sorting network. There is an input for a control signal operative to initiate a sorting of data between the plurality of inputs N and the plurality of outputs M. The data ordering device is coupled to a core of a central processing unit.

Reformatting matrices to improve computing efficiency

A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.

Hardware-based implementation of secure hash algorithms

In response to encountering a function entry instruction while running an application, a processor computes an entry hash value using a hash of three hash input parameters, wherein one of the input parameters is a secret key stored in the special purpose register. In response to encountering a function exit instruction, the processor computes an exit hash value using the same three input parameters and the same hash used when computing the entry hash value. The processor determines if the entry hash value is the same as the exit hash value. In response to the entry hash value being the same as the exit hash value the processor exits the function and in response to the entry hash value not being the same as the exit hash value the processor executes a trap interrupt.

Comparing hash values computed at function entry and exit for increased security

Aspects of the present disclosure relate to encrypted data processing (EDAP). Encrypted data from a cache to be loaded into a register file can be accessed. The encrypted data can be decrypted to receive cleartext data. The cleartext data can be written to the register file. The cleartext data can be processed using at least one functional unit to receive cleartext computation results. The cleartext computation results can then be written back to the register file.

Encrypted data processing design including cleartext register files

An apparatus, system and method for protecting the confidentiality and integrity of a secure object running on a computer system by protecting the memory pages owned by the secure object, including assigning a secure object an ID, labeling the memory pages owned by a secure object with the ID of the secure object, maintaining an Access Control Monitor (ACM) table for the memory pages on the system, controlling access to memory pages by monitoring load and store instructions and comparing information in the ACM table with the ID of the software that is executing these instructions; and limiting access to a memory page to the owner of the memory page.

System and method for supporting secure objects using a memory access control monitor

A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with a single register tag, write the register tag into a mapper with bits indicating that the register tag is for a first instruction of the two instructions, write the register tag into the mapper with bits indicating that the register tag is for a second instruction of the two instructions, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation units (VSU), and execute the two instructions.

Loosely-coupled slice target file data

Aspects of the present disclosure relate to encrypted data processing (EDAP). A processor includes a register file configured to store ciphertext data, an instruction fetch and decode unit configured to fetch and decode instructions, and a functional unit configured to process the stored ciphertext data. The functional unit further includes a decryption module configured to decrypt ciphertext data from the register file to receive cleartext data using an encryption key stored within the functional unit. The functional unit further includes a local buffer configured to store the cleartext data. The functional unit further includes an arithmetic logical unit configured to generate cleartext computation results using the cleartext data The functional unit further includes an encryption module configured to encrypt the cleartext computation results to generate ciphertext computation results for storage back into the register file.

Encrypted data processing design including local buffers

Embodiments for providing memory access operations for graph analytics by a processor are disclosed. An entire chunk of load and store instructions may be atomically and concurrently executed, where the entire chunk of the load and store instructions are delineated from a plurality of alternative load and store instructions.

Memory access operations for large graph analytics

A Reduced Instruction Set Computer ('RISC') supporting large-word operations in a computing environment is disclosed. In one implementation, in response to receiving one or more control signals from a central processing unit ('CPU'), a set of operations are executed on a state of a special purpose execution unit (&#x201c;SPU&#x201d;) having a plurality of SPU registers, the SPU being associated with the CPU and the state of the SPU having word widths of one or more of the plurality of registers being greater in size than word widths of a plurality of CPU registers of a computing system and a set of state-master bits to synchronize the state of the SPU and a state of the CPU. The results of the set of operations are stored in the plurality of CPU registers or an alternative set of the plurality of SPU registers.

Supporting large-word operations in a reduced instruction set computer ('RISC') processor

Method and systems for creating a sequence of fused instructions. An instruction stream is obtained, and a window of instructions from the instruction stream is examined and one or more groups of instructions that satisfy one or more fusion rules are identified. One or more of the groups of instructions that satisfy the one or more fusion rules are fused and a maximal length data dependence chain in the instruction stream is analyzed by analyzing every node in a dependence graph in a selected window of instructions. Fusion of an instruction group is prevented based on the maximal length data dependence chain.

Instruction fusion using dependence analysis

An instruction fusion system in which instructions are tagged with extra bits to specify the conditions by which the instructions can be fused is provided. A computing device receives a first instruction to be executed at a processor. The computing device receives a first fusion tag that corresponds to the first instruction, the first fusion tag specifying a condition for fusing the first instruction with another instruction. The computing device determines whether the first instruction is allowed to fuse with a second instruction based on the first fusion tag. When the first instruction is allowed to fuse with the second instruction, the computing device generates a fused instruction based on the first instruction and the second instruction. The computing device executes the fused instruction at the processor.

Mechanism for instruction fusion using tags

A computing system includes a plurality of functional units, each functional unit having one or more inputs and an output. There is a shared memory block coupled to the inputs and outputs of the plurality of functional units. There is a private memory block assigned to each of the plurality of functional units. An inter functional unit data bypass (IFUDB) block is coupled to the plurality of functional units. The IFUDB is configured to route signals between the one or more functional units without use of the shared memory block.

Processor core design optimized for machine learning applications

A processor core and methods for managing the processor core. The processor core comprises of a plurality of lanes, each lane comprising a copy of a register file logically shared across the plurality lanes and a plurality of functional units, at least two of the functional units sharing a common cache and a common control unit, where the common control unit concurrently dispatches multiple consecutive instances of an instruction corresponding to multiple successive instances of an inner loop to the plurality of functional units of at least a proper subset of the plurality of lanes; and one or more registers of each copy of the register file, each register being configurable to write a data result from at least one of the functional units to a register in a lane-local mode, a lane-forward mode, and a normal mode.

Efficient performance of inner loops on a multi-lane processor

A processor in a computer system, the processor including a mechanism supporting a Secure Object that comprises information that is protected so that other software on said computer system cannot access or undetectably tamper with said information, thereby protecting both a confidentiality and an integrity of the Secure Object information while making the Secure Object information available to the Secure Object itself during execution of the Secure Object. The mechanism includes a crypto mechanism that decrypts and integrity-checks Secure Object information as said Secure Object information moves into the computer system from an external storage system, and encrypts and updates an integrity value for Secure Object information as said Secure Object information moves out of the computer system to the external storage system, and a memory protection mechanism that protects the confidentiality and integrity of Secure Object information when that information is in the memory of the computer system.

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Mohegan Lake, NY, United States of America

Kattamuri Ekanadham