Sanken Electric Co., Ltd.

Katsuyuki Torii

Ryoji Takahashi

Masaki Kanazawa

Satoshi Kawashiri

Yuya Maekawa

Arata Shiomi

A semiconductor device according to one or more embodiments may include a drive circuit comprising: a gate control circuit that generates a gate control signal; a first resistor comprising a first electrode electrically connected to the gate control circuit and a second electrode; and a second resistor comprising a first electrode electrically connected to the gate control circuit and a second electrode that is not electrically connected to the second electrode of the first resistor; wherein the second resistor comprises a resistance value greater than that of the first resistor; an IGBT circuit comprising: a first IGBT cell electrically connected to the second electrode of the first resistor; and a second IGBT cell electrically connected to the second electrode of the second resistor.

Semiconductor device

A semiconductor device may include: a drift region of a first conductivity type; a base region of a second conductivity type arranged on the drift region; an emitter region of the first conductivity type arranged on the base region; a field stop region of the first conductivity type arranged in contact with the drift region; a collector region of the second conductivity type in contact with the field stop region; a main gate electrode electrically insulated from the base region and the collector region; a control gate electrode electrically insulated from the base region and the collector region; a gate pad on the drift region; a first resistor electrically connected between the gate pad and the main gate electrode; and a second resistor electrically connected between the gate pad and the control gate electrode. A resistance value of the first resistor may be greater than the second resistor thereof.

A semiconductor device includes a switching element chip, in which a switching element is formed; a first sensing element, which is provided in the switching element chip and is configured to detect first output voltage based on an operating current of the switching element; a second sensing element, which is provided outside the switching element chip and is configured to detect second output voltage based on the operating current of the switching element; and a control circuit, which detects the operating current based on the second output voltage and interrupts the switching element, based on the first output voltage of the first sensing element and the detected operating current, when the switching element is overheated.

Semiconductor device and control method thereof

A semiconductor device includes: a first conductivity-type collector region; a second conductivity-type field stop region disposed on the collector region; a second conductivity-type drift region, which is disposed on the field stop region and has an impurity concentration lower than the field stop region; a first conductivity-type base region disposed on the drift region; and a second conductivity-type emitter region disposed on the base region, wherein an impurity concentration gradient in a film thickness direction of the field stop region is larger in a region adjacent to the collector region than in a region adjacent to the drift region.

A semiconductor device includes: a first semiconductor region; a second semiconductor region; a third semiconductor region; a fourth semiconductor region; an insulation film, which is arranged on an inner wall of a recess extending from an upper surface to the second semiconductor region; a control electrode, which is arranged on a region of the insulation film on a side surface of the recess; a first main electrode connected to the first semiconductor region; a second main electrode connected to the fourth semiconductor region; and a bottom electrode, which is arranged on the insulation film and is electrically connected to the second main electrode, and a length of the recess in an extension direction thereof is equal to or larger than a width of the recess, and the width of the recess is wider than an interval between the adjacent recesses.

Semiconductor device with bottom gate wirings

A semiconductor device includes a p-type collector region, a drift region arranged on the collector region, a base region arranged on the drift region, an emitter region arranged on the base region, a gate oxide film arranged on the bottom surface and side surface of a trench which penetrates the emitter region and the base region, and a gate electrode embedded in the inside of the trench so as to be opposed to the base region while interposing the gate oxide film therebetween, wherein the position of the lower surface of the base region is shallower in the region brought into contact with the gate oxide film than in the region spaced apart from the gate oxide film.

Semiconductor device and method for manufacturing the semiconductor device

An IGBT having a good balance between high switching speed and low on-resistance. Specifically disclosed is an IGBTin which a defect layeris formed in an n layerin an active regionand formed in a p-type substratein a non-active region. In other words, the defect layerin the active regionis at a shallower position than the defect layerin the non-active regionwhen viewed from the surface. Due to this configuration, the switching speed is increased by reducing the amount of holes injected in the non-active regionin the IGBT. Meanwhile, the reduction of hole injection amount in the active regionis smaller than that in the non-active region, and thus increase in the on-resistance is suppressed at that time.

Semiconductor device and method for manufacturing same

The present invention provides a semiconductor device and manufacturing method of the semiconductor device which can prevent breaks in an interlayer insulation film () and electrode () that arise with bonding while maintaining bonding strength. A semiconductor element () mounted on a semiconductor device including an interlayer insulation film () which has an aperture part () having an opening shape which is defined by an extension part () which covers the gate electrode () and extends in the first direction, a connection part (), the extension part () and the connection part () which connects at fixed intervals in the first direction a pair of extension parts () which are adjacent to the second direction, and which exposes a main surface of a base region () and a main surface of an emitter region (). Also, a second width dimension (W) in the first direction below the connection part () is larger than a first width dimension (W) in the second direction of the emitter region () below the extension part () of the interlayer insulation film ().

Semiconductor device and manufacturing method thereof

Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region of the N-type to form a diode and a diode electrode that is formed on an upper face of the peripheral section of the first base region, thereby electrically connecting the diode electrode and a collector electrode of each of the IGBTs. When the semiconductor device is ON, current flows at the center side of the semiconductor substrate separated from the side face. When current in a reverse direction is generated when the semiconductor device is OFF, current in a reverse direction flows in the vicinity of the side face of the semiconductor substrate.

Semiconductor device having a stacked multi structure that has layered insulated gate-type bipolar transistors

A semiconductor devicecomprises a P type base regionformed in an Ntype base region, and Ntype emitter regionsformed plurally in the P type base regionso as to be spaced form each other. The Ntype emitter regionsare formed such that the rate of the area occupied by the Ntype emitter regionin the P type base regionat the center part of the semiconductor deviceis smaller than the rate of the area occupied by the Ntype emitter regionin the P type base regionat the peripheral part of the semiconductor device

A semiconductor deviceincludes a first transistorplaced on a substrate, a second transistorplaced on the first transistorvia a heat radiation layer, a third transistorplaced on the substrate, and a fourth transistorplaced on the third transistorvia a heat radiation layer. The first transistorhas a first region corresponding to a region where the second transistor is placed, and a second region which is formed so as to surround the first region and in which the rate of area occupied by the emitter region in the base region is higher than in the first region. Likewise the first transistor, the third transistorhas a region in which the rate of area occupied by the emitter region in the base region is varied.

Semiconductor device having plural regions and elements with varying areas depending on the region

A reliable semiconductor device is provided which comprises lower and upper IGBTsandpreferably bonded to each other by solder, and a wire strongly connected to lower IGBT. The semiconductor device comprises a lower IGBT, a lower electrode layersecured on lower IGBT, an upper electrode layersecured on lower electrode layer, an upper IGBTsecured on upper electrode layer, and a solder layerwhich connects upper electrode layerand upper IGBT. Lower and upper electrode layersandare formed of different materials from each other, and upper electrode layerhas a notchto partly define on an upper surfaceof lower electrode layera bonding regionexposed to the outside through notchso that one end of a wireis connected to bonding region. Upper electrode layercan be formed of one material superior in soldering, and also, lower electrode layercan be formed of another material having a high adhesive strength to wire

Semiconductor device and its manufacture

An IGBT is disclosed which has a set of inside trenches and an outside trench formed in its semiconductor substrate. The substrate has emitter regions adjacent the trenches, a p-type base region adjacent the emitter regions and trenches, and an n-type base region comprising a first and a second subregion contiguous to each other. The first subregion of the n-type base region is contiguous to the inside trenches whereas the second subregion, less in impurity concentration than the first, is disposed adjacent the outside trench. Breakdown is easier to occur than heretofore adjacent the inside trenches, saving the device from destruction through mitigation of a concentrated current flow adjacent the outside trench.

Trenched semiconductor device

An insulated gate bipolar transistor has a P-type collector region containing a P-type impurity such as boron. A relatively thin N-type buffer region containing arsenic in a relatively high concentration is formed on the collector region via an anti-diffusion region. The anti-diffusion region is provided in such a way that its thickness is the same as or slightly smaller than the distance over which the P-type impurity is diffused from the collector region toward the buffer region in a device fabrication process.

Insulated gate bipolar transistor having a high switching speed and method for fabricating the same

An IGBT has an N-type buffer region between a P-type collector region and a P-type base region. The buffer region includes arsenic as a N-type impurity. The buffer region is formed to have a relatively high impurity concentration of equal to or greater than 5&#xd7;1017 cm-3 and a relatively small thickness of 2 to 10 &#x3bc;m.

Growing community of inventors

Niiza, Japan

Katsuyuki Torii