Nec Corporation

Honda Motor Co., Ltd.

Tdk Corporation

Jeol Ltd.

Mitsuba Corporation

Katsuyuki Suzuki

Hiroshi Suzuki

Toshio Tomonari

Akira Sato

Toshihiro Kuroshima

Koji Okabe

Kazutada Sasaki

Takeshi Sasaki

Masaaki Kimura

Takeshi Kanai

Katsumi Saito

Yuki Takahashi

Douglas J Duff

Takashi Komoriya

Yutaro Takahashi

Yoshinobu Noro

Andy Sweigart

Provided is an observation method including: acquiring an observed image that has been photographed by the first specimen observation apparatus with the specimen holder being mounted on the first specimen stage, the observed image having an observation target position of a specimen positioned at a center thereof, and including the plurality of markers (Step S); acquiring pixel coordinates of each of the plurality of markers in the observed image (Step S); acquiring stage coordinates of each of the plurality of markers on the second specimen stage having the specimen holder mounted thereon (Step S); and converting, based on the pixel coordinates of the plurality of markers and the stage coordinates of the plurality of markers, pixel coordinates of the center of the observed image into stage coordinates to move the second specimen stage to the obtained stage coordinates (Step S).

Observation method and specimen observation apparatus

An object of the present invention is to provide a wiper apparatus reduced in the number of parts. A wiper apparatusA has: a drive mechanismfor driving a wiperfor wiping a front windshield of a vehicle; a gear casein which the drive mechanismis housed, and which is fixed to a vehicle body, wherein the wiper apparatusA has: a fixing partprovided in the gear caseand fixed to the vehicle body; and a fixing partprovided in the gear caseand fixed to the vehicle body at a position different from a fixed position of the fixing partin a longitudinal direction of the vehicle body.

Wiper apparatus

Sealing member seals a through-hole formed in a panel that defines first and second compartments of a vehicle, and it has a tubular section and stopper portions. The intercompartment sealing member is fit onto a receiving member provided in the first compartment. Lip section, extending from the tubular section toward the panel in a spread-out form, is bendable (reversible) with respect to the panel. The lip section has operating convexities provided on its panel-facing surface. Manipulation of the operating convexities can invert the lip section, initially bent away from the panel, to contact the panel. The stopper portions function to limit a bent amount through which the lip section can be bent away from the panel (in the reverse direction).

Intercompartment sealing member for vehicle

A common-mode filter with a drum type core including a core portion and flange portions. Electrodes are provided on the flange portions and a pair of wires are wound on the core portion. The wound pair of wires have ends connected to respective ones of the electrodes. Each of the flange portions has a groove between corresponding two of the electrodes and a separation protrusion for separating the groove into two lead-out groove portions. The pair of wires are wound on the core portion in such a distributed winding manner that an inter-wire distance between the pair of wires and a winding pitch between adjacent turns in each of the pair of wires are provided. The wires are one-by-one led out through the lead-out groove portions while separated by the separation protrusions so that the ends of the pair of wires are connected to respective electrodes.

Common-mode filter

A crossbar switch system with redundancy has N+1 cross-bar switches. A first cross-bar switch has first outputs of each of a plurality of nodes applied to N input terminals thereof, an (N+1)th cross-bar switch has Nth outputs of each of the nodes applied to N input terminals thereof, and second to Nth (Ith) cross-bar switches each have first to Nth selection circuits, which are provided at respective input terminals thereof, to each of which are input mutually adjacent (I&#x2212;1)th and Ith outputs among outputs of each of the nodes. Each (Jth) node has N selection switches, which are provided at input terminals thereof, to each of which are input Jth outputs of two mutually adjacent cross-bar switches among the first to (N+1)th cross-bar switches. In response to a selection control signal output from a failure processing circuit that executes crossbar switch failure processing, each of the selection circuits selects and outputs one of its two inputs.

Cross-bar switch system with redundancy

A semiconductor chip of the present invention includes a plurality of first elements each of which diagnoses itself, and a second element which inputs diagnosis results from the first elements and determines whether or not there is a faulty first element in the first elements. A method of the present invention which is performed in a semiconductor chip including a plurality of first elements, includes diagnosing the first elements by itself; and determining whether or not there is a faulty first element in the first elements based on diagnosis results from the first elements.

Initializing/diagnosing system in on-chip multiprocessor system

A predetermined number of logical page addresses are effectively translated into corresponding real ones. The number of the logical page addresses is determined by (M+N) bits and, each of the logical page addresses includes upper M-bit and lower N-bit. Logical page address registers, whose number is equal to 2.sup.N, are provided to respectively store the predetermined number of logical page addresses applied. Address translation buffers (whose number is also equal to 2.sup.N) each stores 2.sup.M real page addresses which are grouped according to each of the lower N bits. The address translation buffers receive the upper M-bit of one of the logical page addresses, and output real addresses. An address translation controller receives the outputs of the address translation buffers and also receives the lower N-bit, and selects the real page addresses using the lower N-bit. The selected real page addresses are applied to a plurality of real address registers. A page number comparator determines whether or not the upper M-bit of one of the logical page address coincides with the upper M-bit of each of the remaining logical page addresses. The page number comparator outputs the comparison results which allow the real address(es) stored in the real address registers to be applied to a main memory.

Arrangement for simultaneously translating logical page addresses to

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Tokyo, Japan

Katsuyuki Suzuki