Kabushiki Kaisha Toshiba

Katsuyuki Kimura

Tatsuya Mori

Yoshimichi Tanizawa

Takashi Miyamori

Yasuki Tanabe

Keiri Nakanishi

Masato Sumiyoshi

Ryuji Hada

Shunichi Ishiwata

Takahisa Wada

Yasukazu Okamoto

Keisuke Mera

Koji Kanazawa

Kazuhiro Hiwada

Tsuyoshi Nakano

According to one embodiment, an image processing device includes a shift estimator, and a de-mosaic module. The shift estimator is configured to estimate a shift amount between a first pixel in a first image and a corresponding second pixel in a second image. The first image is taken by a first image pickup apparatus, and the second image is taken by a second image pickup apparatus. A focus position of the first image pickup apparatus is different from a focus position of the second image pickup apparatus. The de-mosaic module is configured to generate a first de-mosaic image by performing de-mosaic processing on each pixel in the first pixel using a pixel value of the corresponding second pixel, when the first pixel is determined to be in a state of in-focus based on the shift amount.

Image processing device and image processing system where de-mosaic image is generated based on shift amount estimation of pixels of captured images

According to one embodiment, an image processing apparatus connectable to a main memory in which a plurality of pixel values of unconverted image is stored and a cache memory including a plurality of cache blocks. The apparatus includes a counter, a coordinate determination module, a memory controller, a cache access module, a pixel value calculator, and an output module. The counter determines a coordinate within converted image according to a predetermined execution sequence. The coordinate determination module determines a plurality of coordinates within unconverted image of the pixel values of unconverted image necessary to calculate a pixel value of converted image corresponding to the coordinate within converted image. The memory controller transfers the pixel values of unconverted image stored in the main memory to the cache blocks corresponding to each of the coordinates within unconverted image. The cache access module reads out all the pixel values of unconverted image necessary to calculate the pixel value of converted image from the cache blocks. The pixel value calculator calculates the pixel value of converted image by referring to the pixel values of unconverted image read out by the cache access module. The output module outputs the pixel value of converted image.

Image processing apparatus, image processing system, and method for having computer process image

An image processor includes a video input unit that counts the number of input pixel data and a command fetch/issue unit calculates, when a command including information concerning a relative position register in which a delay amount from input of pixel data until execution of a command is stored is fetched, a pixel position of processing target pixel data based on the delay amount and a count result and determines, based on the calculated pixel position, whether signal processing should be performed or specifies an operand used in arithmetic operation.

Image processor and command processing method

According to one embodiment, an image processing apparatus connected to an external memory and a cache memory. The apparatus includes a counter, a coordinate calculator, a tag checker, a pixel referring module, a pixel value calculator and an outputting module. The counter determines a converted coordinate according to a predetermined execution sequence. The coordinate calculator calculates a unconverted coordinate used to calculate a converted pixel value located at the converted coordinate. The tag checker generates a conversion request to calculate the converted pixel value with reference to an unconverted pixel located at the unconverted coordinate. The pixel referring module reads the unconverted pixel from the cache memory based on the conversion request when the unconverted pixel is stored in the cache memory. The pixel value calculator calculates the converted pixel value with reference to the read unconverted pixel. The outputting module writes the converted pixel having the calculated converted pixel value into the external memory.

Image processing apparatus and image processing system

According to an embodiment, a compiling device compiling a source program written so as to use a frame memory includes a processing delay amount calculator configured to calculate respective processing delay amounts between a plurality of process tasks in the source program on the basis of processing states of pieces of data processed by the process tasks. The compiling device also includes a line memory amount calculator configured to calculate respective line memory sizes required for each of the process tasks on the basis of an access range of a frame memory from which the process task reads data and an instruction code converter configured to convert the plurality of process tasks to instruction codes executable in a pipeline on the basis of the processing delay amounts and the line memory sizes.

Compiling device and compiling method

An image processing apparatus has: a data memory configured to store image data; an RP register configured to hold a two-dimensional address indicating a position of an RP in a frame of image data; and an RP control section configured to control the two-dimensional address held by the RP register on the basis of the width and height of the frame. Furthermore, the image processing apparatus has an address calculation unit configured to, when reading target pixel data is read from the data memory on the basis of an instruction code provided with a field for specifying a two-dimensional relative position from the RP by a combination of two immediate values, calculate an address at which the reading target pixel data is stored, on the basis of the two-dimensional address, the combination of immediate values and the width of the frame.

A memory controller, on receiving a write request to write write-data into an address of a second memory region issued by a processor, determines whether read-data requested to be read from an address of a first memory region by the processor is matched with the write-data requested to be written into the address of the second memory region, and if the read-data is matched with the write-data, prevents the write-data from being written into the address of the second memory region.

Memory controller

A trace analyzing apparatus, which includes a trace analysis table, an instruction reconstruction unit that reconstructs and sends an execution address and an instruction code of trace information, and an object code list storage unit, reads out an object code list and trace information, captures each piece of information in reverse order from the last stored address information stored in an address register, and then registers them in the trace analysis table.

Trace analyzing apparatus, trace analyzing method, and processor

A microprocessor a microprocessor includes: a processor module executing an instruction to generate trace information including the information of the kind and the length of the instruction; an application processing circuit operating in cooperation with the processor module to process a specific application; an address calculating circuit calculating an execution address for executing the instruction based on the information of the instruction length; a data obtaining circuit obtaining data from the application processing circuit when the calculated execution address is located within a range of a designated address; and a trace memory in which the obtained data is stored together with the trace information.

Microprocessor and processing method thereof

A tracer includes a trace memory that is stored with trace information of the program execution status of a processor; trace information compression unit that compresses the trace information into a predetermined trace format, and stores the resulting compressed information in the trace memory piece by piece cyclically; and an address register that stores the last stored address of the trace memory, analyzes the content of the trace memory in reverse order to a program executed order, searches for a start or end of the trace format, and carries out trace analysis therefrom in the program executed order.

Growing community of inventors

Kamakura, Japan

Katsuyuki Kimura